Zynq UltraScale+ RFSoC
Data Sheet: Overview
DS889 (v1.5) July 23, 2018
Advance Product Specification
General Description
The Zynq® UltraScale+™ RFSoC family integrates key subsystems for multiband, multi-mode cellular
radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bit
quad-core ARM® Cortex™-A53 and dual-core ARM Cortex-R5 based processing system.
Combining the processing system with UltraScale™ architecture programmable logic and RF-ADCs,
RF-DACs, and soft-decision FECs, the Zynq UltraScale+ RFSoC family is capable of implementing a
complete software-defined radio including direct RF sampling data converters, enabling CPRI™ and
gigabit Ethernet-to-RF on a single, highly programmable SoC.
Zynq UltraScale+ RFSoCs integrate up to 16 channels of RF-ADCs and RF-DACs. The RF-ADCs can sample
input frequencies up to 4GHz at 4.096GSPS with excellent noise spectral density. The RF-DACs generate
output carrier frequencies up to 4GHz using the 2nd Nyquist zone with excellent noise spectral density at
an update rate of 6.554GSPS. The RF data converters also include power efficient digital down converters
(DDCs) and digital up converters (DUCs) that include programmable interpolation and decimation, NCO,
and complex mixer. The DDCs and DUCs can also support dual-band operation.
The soft-decision FEC (SD-FEC) is a highly flexible forward error correction engine capable of operating in
Turbo decoding mode for wireless applications such as LTE and LDPC encode/decode mode used in 5G
wireless, backhaul, and DOCSIS 3.1 cable modems.
Key Components of the Zynq UltraScale+ RFSoC
X-Ref Target - Figure 1
Up to 16 Channels
Processing System
Quad Arm Cortex-A53
Dual Arm Cortex-R5
DDC
RF-ADC
RF-ADC
RF In
Up to 16 Channels
CPRI
10/40/100 GE
GTY
Transceiver
SD-FEC
DUC
RF-DAC
RF Out
RF-DAC
Programmable Logic
DS889_01_072318
Figure 1:
Zynq UltraScale+ RFSoC
© Copyright 2017–2018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the
EU and other countries. CPRI is a trademark of Siemens AG. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the
DS889 (v1.5) July 23, 2018
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Zynq UltraScale+ RFSoC Data Sheet: Overview
Summary of Features
RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio
frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog
converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be
individually configured for real data or can be configured in pairs for real and imaginary I/Q data. The
12-bit RF-ADCs support sample rates up to 2.058GSPS or 4.096GSPS, depending on the selected device.
The 14-bit RF-DACs support sample rates up to 6.554GSPS.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding
data as a means to control errors in data transmission over unreliable or noisy communication channels.
The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in
5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ RFSoCs feature a quad-core ARM Cortex-A53 (APU) with a dual-core ARM Cortex-R5
(RPU) processing system (PS).
To support the processors' functionality, a number of peripherals with dedicated functions are included in
the PS. For interfacing to external memories for data or configuration storage, the PS includes a
multi-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller
and a Quad SPI controller. In addition to interfacing to external memories, the APU also includes a Level-1
(L1) and Level-2 (L2) cache hierarchy; the RPU includes an L1 cache and Tightly Coupled memory
subsystem. Each has access to a 256KB on-chip memory.
For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs of
transceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can
interface to the high-speed peripheral blocks to support PCIe® Gen2 root complex or Endpoint in x1, x2,
or x4 configurations; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; and up to two lanes of
DisplayPort at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers can also interface to
components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII).
For general connectivity, the PS includes: a pair of USB 2.0 controllers, which can be configured as host,
device, or On-The-Go (OTG); an I2C controller; a UART; and a CAN2.0B controller that conforms to
ISO11898-1. There are also four triple speed Ethernet MACs and 128 bits of GPIO, of which 78 bits are
available through the MIO and 96 through the EMIO.
High-bandwidth connectivity based on the ARM AMBA® AXI4 protocol connects the processing units with
the peripherals and provides interface between the PS and the programmable logic (PL).
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Zynq UltraScale+ RFSoC Data Sheet: Overview
I/O, Transceiver, PCIe, 100G Ethernet, and 150G Interlaken
Data is transported on and off chip through a combination of the high-performance parallel SelectIO™
interface and high-speed serial transceiver connectivity. I/O blocks provide support for cutting-edge
memory interface and network protocols through flexible I/O standard and voltage support. The serial
transceivers in the UltraScale architecture-based devices transfer data up to 32.75Gb/s, enabling 25G+
backplane designs with dramatically lower power per bit than previous generation transceivers. The GTY
transceivers support the required data rates for PCIe Gen3, and Gen4 (rev 0.5), and integrated blocks for
PCIe enable Zynq UltraScale+ RFSoCs to support up to Gen4 x8 and Gen3 x16 Endpoint and Root Port
designs. Integrated blocks for 150Gb/s Interlaken and 100Gb/s Ethernet (100G MAC/PCS) extend the
capabilities of UltraScale™ devices, enabling simple, reliable support for Nx100G switch and bridge
applications.
Clocks and Memory Interfaces
Zynq UltraScale+ RFSoCs contain powerful clock management circuitry, including clock synthesis,
buffering, and routing components that together provide a highly capable framework to meet design
requirements. The clock network allows for extremely flexible distribution of clocks to minimize the skew,
power consumption, and delay associated with clock signals. The clock management technology is tightly
integrated with dedicated memory interface circuitry to enable support for high-performance external
memories, including DDR4. In addition to parallel memory interfaces, Zynq UltraScale+ RFSoCs support
serial memories, such as hybrid memory cube (HMC).
Routing, Logic, Storage, and Signal Processing
Configurable logic blocks (CLBs) containing 6-input look-up tables (LUTs) and flip-flops, DSP slices with
27x18 multipliers, 36Kb block RAMs with built-in FIFO and ECC support, and 4Kx72 UltraRAM blocks are all
connected with an abundance of high-performance, low-latency interconnect. In addition to logical
functions, the CLB provides shift register, multiplexer, and carry logic functionality as well as the ability to
configure the LUTs as distributed memory to complement the highly capable and configurable block
RAMs. The DSP slice, with its 96-bit-wide XOR functionality, 27-bit pre-adder, and 30-bit A input, performs
numerous independent functions including multiply accumulate, multiply add, and pattern detect.
Configuration, Encryption, and System Monitoring
Zynq UltraScale+ RFSoCs are booted via the configuration security unit (CSU), which supports secure boot
via the 256-bit AES-GCM and SHA/384 blocks. The cryptographic engines in the CSU can be used in the
RFSoC after boot for user encryption. The System Monitor enables the monitoring of the physical
environment via on-chip temperature and supply sensors and can also monitor up to 17 external analog
inputs.
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Zynq UltraScale+ RFSoC Data Sheet: Overview
Zynq UltraScale+ RFSoC Feature Summary
Table 1:
Zynq UltraScale+ RFSoC Feature Summary
XCZU21DR
12-bit, 4.096GSPS RF-ADC w/ DDC
12-bit, 2.058GSPS RF-ADC w/ DDC
14-bit, 6.554GSPS RF-DAC w/ DUC
SD-FEC
Application Processing Unit
Real-Time Processing Unit
Embedded and External Memory
General Connectivity
High-Speed Connectivity
System Logic Cells
CLB Flip-Flops
CLB LUTs
Distributed RAM (Mb)
Block RAM Blocks
Block RAM (Mb)
UltraRAM Blocks
UltraRAM (Mb)
DSP Slices
CMTs
Maximum HP I/O
Maximum HD I/O
System Monitor
GTY Transceivers
Transceivers Fractional PLLs
PCIe Gen3 x16 and Gen4 x8
150G Interlaken
100G Ethernet w/ RS-FEC
0
0
0
8
XCZU25DR
8
0
8
0
XCZU27DR
8
0
8
0
XCZU28DR
8
0
8
8
XCZU29DR
0
16
16
0
Quad-core ARM Cortex-A53 MPCore with CoreSight™; NEON and Single/Double Precision
Floating Point; 32KB/32KB L1 Cache, 1MB L2 Cache
Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating Point; 32KB/32KB
L1 Cache, and TCM
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3; External
Quad-SPI; NAND; eMMC
214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; Watchdog Timers;
Triple Timer Counters
4 PS-GTR; PCIe® Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
930,300
850,560
425,280
13.0
1,080
38.0
80
22.5
4,272
8
208
72
1
16
8
2
1
2
678,318
620,176
310,088
9.6
792
27.8
48
13.5
3,145
6
299
48
1
8
4
1
1
1
930,300
850,560
425,280
13.0
1,080
38.0
80
22.5
4,272
8
299
48
1
16
8
2
1
2
930,300
850,560
425,280
13.0
1,080
38.0
80
22.5
4,272
8
299
48
1
16
8
2
1
2
930,300
850,560
425,280
13.0
1,080
38.0
80
22.5
4,272
8
312
96
1
16
8
2
1
2
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Zynq UltraScale+ RFSoC Data Sheet: Overview
Table 2:
Zynq UltraScale+ RFSoC Device-Package Combinations and Maximum I/Os
XCZU21DR
Package
Dimensions
214, 72, 208
4, 16, 0, 0
214, 48, 104
4, 8, 8, 8
214, 48, 104
4, 8, 8, 8
214, 48, 299
4, 8, 8, 8
214, 48, 299
4, 8, 8, 8
214, 48, 104
4, 8, 8, 8
214, 48, 104
4, 8, 8, 8
214, 48, 299
4, 16, 8, 8
214, 48, 299
4, 16, 8, 8
214, 48, 104
4, 8, 8, 8
214, 48, 104
4, 8, 8, 8
214, 48, 299
4, 16, 8, 8
214, 48, 299
4, 16, 8, 8
214, 96, 312
4, 16, 16, 16
214, 96, 312
4, 16, 16, 16
XCZU25DR
XCZU27DR
XCZU28DR
XCZU29DR
PSIO, HDIO, HPIO,
PS-GTR, GTY, RF-ADC, RF-DAC
FFVD1156
FFVE1156
FSVE1156
FFVG1517
FSVG1517
FFVF1760
FSVF1760
35x35
35x35
35x35
40x40
40x40
42.5x42.5
42.5x42.5
RF Data Converter Subsystem
The RF data converter subsystem comprises RF-ADCs and RF-DACs.
RF-ADC Features
•
Tile oriented
o
o
o
Four RF-ADCs and one PLL per tile
12-bit resolution
Implemented as either 4 channels of 2.058GSPS, or 2 channels of 4.096GSPS (device dependent)
1x, 2x, 4x, 8x
Full bandwidth data-rate support
80% pass band, 89dB stop-band attenuation
Full complex mixers
48-bit NCO per RF-ADC
Fixed Fs/4, Fs/2 low-power mode
2x bands per 2.058GSPS RF-ADC pair
Can be configured for real or imaginary (I/Q) inputs
Two programmable flags per RF-ADC
•
Decimation filters
o
o
o
•
Mixer
o
o
o
•
Single/multiband flexibility
o
o
•
Signal amplitude threshold
o
DS889 (v1.5) July 23, 2018
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