SY10E160JC-TR datasheet, PDF - EEWORLD Datasheet

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SY10E160JC-TR: DescriptionIC 12-BIT GEN/CHKER 28PLCC; Categorysemiconductor logic; File Size60KB，5 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY10E160JC-TR Overview

IC 12-BIT GEN/CHKER 28PLCC

SY10E160JC-TR Parametric

Parameter Name	Attribute value
logical type	Parity generator/checker
Number of circuits	12 bits
Current - output high, low	-
Voltage - Power	4.2V ~ 5.5V
Operating temperature	0°C ~ 85°C
Installation type	surface mount
Package/casing	28-LCC (J-lead)
Supplier device packaging	28-PLCC（11.5x11.5）

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Micrel, Inc.

12-BIT PARITY

GENERATOR/CHECKER

SY10E160

SY100E160

SY10E160

SY100E160

FEATURES

Provides odd-HIGH parity of 12 inputs

Extended 100E V

range of –4.2V to –5.5V

Output register with Shift/Hold capability

900ps max. D to Q, /Q output

Enable control

Asynchronous Register Reset

Differential outputs

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E160

Available in 28-pin PLCC package

DESCRIPTION

The SY10/100E160 are high-speed, 12-bit parity

generator/checkers with differential outputs, for use in

new, high-performance ECL systems. The output Q takes

on a logic HIGH value only when an odd number of inputs

are at a logic HIGH. A logic HIGH on the enable input (EN)

forces the output Q to a logic LOW.

An additional feature of the E160 is the output register.

Two multiplexers and their associated signals control the

data, loading the new parity data or shifting external data

in. To hold the present data, the Hold signal (HOLD) must

be at a logic LOW level. If the HOLD signal is at a logic

HIGH, the data present at the Q output is passed through

the first multiplexer. Taking the Shift signal (SHIFT) to a

logic HIGH will shift the data at the S-IN pin into the output

of the first multiplexer is then passed through to the register.

The register itself is clocked on the rising edge of CLK

or CLK

(or both). The presence of a logic HIGH on the

reset pin (R) forces the register output Y to a logic LOW.

BLOCK DIAGRAM

HOLD

S-IN

SHIFT

CLK

MUX

SEL

MUX

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: F

Amendment: /0

Issue Date: March 2006

SY10E160JC-TR Related Products

	SY10E160JC-TR	SY100E160JZ TR	SY10E160JZ TR	SY10E160JC TR
Description	IC 12-BIT GEN/CHKER 28PLCC	IC 12-bit gen/chker 28plcc	IC 12-bit gen/chker 28plcc	IC 12-bit gen/chker 28plcc
Standard Package	-	750	750	750
Category	-	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)
Family	-	Logic - Parity Generators and Checkers	Logic - Parity Generators and Checkers	Logic - Parity Generators and Checkers
Packaging	-	Tape & Reel (TR)	Tape & Reel (TR)	Tape & Reel (TR)
Logic Type	-	Parity Generator/Checke	Parity Generator/Checke	Parity Generator/Checke
Number of Circuits	-	12-Bi	12-Bi	12-Bi
Voltage - Supply	-	4.2 V ~ 5.5 V	4.2 V ~ 5.5 V	4.2 V ~ 5.5 V
Operating Temperature	-	0°C ~ 85°C	0°C ~ 85°C	0°C ~ 85°C
Mounting Type	-	Surface Mou	Surface Mou	Surface Mou
Package / Case	-	28-LCC (J-Lead)	28-LCC (J-Lead)	28-LCC (J-Lead)
Supplier Device Package	-	28-PLCC	28-PLCC	28-PLCC
Other Names	-	SY100E160JZTRSY100E160JZTR-ND	SY10E160JZTRSY10E160JZTR-ND	SY10E160JCTRSY10E160JCTR-ND

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