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74VHC02FT

Description
IC GATE NOR 4CH 2-INP 14TSSOPB
Categorylogic    logic   
File Size153KB,7 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
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74VHC02FT Overview

IC GATE NOR 4CH 2-INP 14TSSOPB

74VHC02FT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerToshiba Semiconductor
package instructionTSSOP-14
Reach Compliance Codeunknown
Factory Lead Time12 weeks
seriesAHC/VHC/H/U/V
JESD-30 codeR-PDSO-G14
length5 mm
Logic integrated circuit typeNOR GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)13 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
74VHC02FT
CMOS Digital Integrated Circuits Silicon Monolithic
74VHC02FT
1. Functional Description
Quad 2-Input NOR Gate
2. General
The 74VHC02FT is an advanced high speed CMOS 2-INPUT NOR GATE fabricated with silicon gate C
2
MOS
technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and
stable output.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature: T
opr
= -40 to 125
High speed: Propagation delay time = 3.6 ns (typ.) at V
CC
= 5.0 V
Low power dissipation: I
CC
= 2.0
µA
(max) at T
a
= 25
High noise immunity: V
NIH
= V
NIL
= 28 % V
CC
(min)
Power-down protection is provided on all inputs.
Balanced propagation delays: t
PLH
t
PHL
Wide operating voltage range: V
CC(opr)
= 2.0 to 5.5 V
Low noise: V
OLP
= 0.8 V (max)
(10) Pin and function compatible with the 74 series (AC/HC/AHC/LV etc.) 02 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4. Packaging
TSSOP14B
Start of commercial production
©2016 Toshiba Corporation
1
2013-11
2016-07-07
Rev.5.0

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