Product Obsolete/Under Obsolescence
0
R
Virtex™ 2.5 V
Field Programmable Gate Arrays
0
0
DS003-1 (v4.0) March 1, 2013
Product Specification
Features
•
Fast, high-density Field Programmable Gate Arrays
- Densities from 50k to 1M system gates
- System performance up to 200 MHz
- 66-MHz PCI Compliant
- Hot-swappable for Compact PCI
Multi-standard SelectIO™ interfaces
- 16 high-performance interface standards
- Connects directly to ZBTRAM devices
Built-in clock-management circuitry
- Four dedicated delay-locked loops (DLLs) for
advanced clock control
- Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
Hierarchical memory system
- LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
- Configurable synchronous dual-ported 4k-bit
RAMs
- Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
•
Supported by FPGA Foundation™ and Alliance
Development Systems
- Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
- Wide selection of PC and workstation platforms
SRAM-based in-system configuration
- Unlimited re-programmability
- Four programming modes
0.22
μm
5-layer metal process
100% factory tested
•
•
•
•
•
Description
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22
μm
CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in
Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
•
•
Table 1:
Virtex Field Programmable Gate Array Family Members
Device
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
System Gates
57,906
108,904
164,674
236,666
322,970
468,252
661,111
888,439
1,124,022
CLB Array
16x24
20x30
24x36
28x42
32x48
40x60
48x72
56x84
64x96
Logic Cells
1,728
2,700
3,888
5,292
6,912
10,800
15,552
21,168
27,648
Maximum
Available I/O
180
180
260
284
316
404
512
512
512
Block RAM
Bits
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
Maximum
SelectRAM+™ Bits
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
© 2001-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v4.0) March 1, 2013
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
Product Obsolete/Under Obsolescence
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Virtex Architecture
Virtex devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex family to accommodate even the largest and most
complex designs.
Virtex FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. In
some modes, the FPGA reads its own configuration data
from an external PROM (master serial mode). Otherwise,
the configuration data is written into the FPGA (Select-
MAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation™ and Alliance Series™
Development systems deliver complete design support for
Virtex, covering every aspect from behavioral and sche-
matic entry, through simulation, automatic design transla-
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream.
Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
internally at speeds in excess of 100 MHz and can achieve
200 MHz.
Table 2
shows performance data for representa-
tive circuits, using worst-case timing parameters.
Table 2:
Performance for Common Circuit Functions
Function
Register-to-Register
Adder
Pipelined Multiplier
Address Decoder
16:1 Multiplexer
Parity Tree
9
18
36
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
200 MHz
180 MHz
16
64
8x8
16 x 16
16
64
5.0 ns
7.2 ns
5.1 ns
6.0 ns
4.4 ns
6.4 ns
5.4 ns
4.1 ns
5.0 ns
6.9 ns
Bits
Virtex -6
Higher Performance
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous
system clock rates up to 200 MHz including I/O. Virtex
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or
66 MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.
Module 1 of 4
2
www.xilinx.com
1-800-255-7778
DS003-1 (v4.0) March 1, 2013
Product Specification
Product Obsolete/Under Obsolescence
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Device/Package Combinations and Maximum I/O
Table 3:
Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
Package
CS144
TQ144
PQ240
HQ240
BG256
BG352
BG432
BG560
FG256
FG456
FG676
FG680
176
176
176
260
176
284
312
404
444
512
444
512
512
180
180
180
260
180
260
260
316
316
404
316
404
316
404
404
XCV50
94
98
166
XCV100
94
98
166
166
166
166
166
166
166
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
Virtex Ordering Information
Example:
Device Type
Speed Grade
-4
-5
-6
XCV300 -6 PQ 240 C
Temperature Range
C = Commercial (T
J
= 0°C to +85°C)
I = Industrial (T
J
= –40°C to +100°C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine-pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
HQ = High Heat Dissipation QFP
TQ = Thin Quad Flat Pack
CS = Chip-scale Package
Figure 1:
Virtex Ordering Information
DS003-1 (v4.0) March 1, 2013
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
3
Product Obsolete/Under Obsolescence
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Revision History
Date
11/98
01/99-02/99
05/99
05/99
07/99
Version
1.0
1.2-1.3
1.4
1.5
1.6
Initial Xilinx release.
Both versions updated package drawings and specs.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
IJITCC
parameter, changed T
OJIT
to
T
OPHASE
.
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
CCO
in CS144 package on p.43.
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
Modified “Pins not listed...” statement. Speed grade update to Final status.
Modified Table 18.
•
•
•
•
•
04/01
03/13
2.5
4.0
•
•
Added XCV400 values to table under
Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under
IOB Input Switching Characteristics.
Added values to table under
CLB SelectRAM Switching Characteristics.
Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
Corrected
BG256 Pin Function Diagram.
Revised minimums for
Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See
Virtex Data Sheet
section.
Revision
09/99
1.7
01/00
1.8
01/00
1.9
03/00
05/00
05/00
09/00
2.0
2.1
2.2
2.3
10/00
2.4
The products listed in this data sheet are obsolete. See
XCN10016
for further information.
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
•
•
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
•
•
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
Module 1 of 4
4
www.xilinx.com
1-800-255-7778
DS003-1 (v4.0) March 1, 2013
Product Specification
Product Obsolete/Under Obsolescence
0
R
Virtex™ 2.5 V
Field Programmable Gate Arrays
0
0
DS003-2 (v4.0) March 1, 2013
Product Specification
The output buffer and all of the IOB control signals have
independent polarity controls.
Architectural Description
Virtex Array
The Virtex user-programmable gate array, shown in
Figure 1,
comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks
(IOBs).
•
•
CLBs provide the functional elements for constructing
logic
IOBs provide the interface between the package pins
and the CLBs
DLL
IOBs
VersaRing
DLL
VersaRing
VersaRing
BRAMs
BRAMs
IOBs
IOBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex architecture also includes the following circuits
that connect to the GRM.
•
•
•
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
CLBs
VersaRing
DLL
IOBs
DLL
vao_b.eps
Figure 1:
Virtex Architecture Overview
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Two
forms of over-voltage protection are provided, one that per-
mits 5 V compliance, and one that does not. For 5 V compli-
ance, a Zener-like structure connected to ground turns on
when the output rises to approximately 6.5 V. When PCI
3.3 V compliance is required, a conventional clamp diode is
connected to the output supply voltage, V
CCO
.
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each pad. Prior to con-
figuration, all pins not involved in configuration are forced
into their high-impedance state. The pull-down resistors and
the weak-keeper circuits are inactive, but inputs can option-
ally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will float.
Consequently, external pull-up or pull-down resistors must
be provided on pins required to be at a well-defined logic
level prior to configuration.
All Virtex IOBs support IEEE 1149.1-compatible boundary
scan testing.
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex IOB,
Figure 2,
features SelectIO™ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see
Table 1.
The three IOB storage elements function either as edge-trig-
gered D-type flip-flops or as level sensitive latches. Each
IOB has a clock signal (CLK) shared by the three flip-flops
and independent clock enable signals for each flip-flop.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
© 1999-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-2 (v4.0) March 1, 2013
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
1
京公网安备 11010802033920号
EEWORLD
