a
FEATURES
8-Bit CMOS DAC with Output Amplifiers
Operates with Single or Dual Supplies
Low Total Unadjusted Error:
Less Than 1 LSB Over Temperature
Extended Temperature Range Operation
P-Compatible with Double Buffered Inputs
Standard 18-Pin DIPs, and 20-Terminal Surface
Mount Package and SOIC Package
LC MOS
8-Bit DAC with Output Amplifiers
AD7224
FUNCTIONAL BLOCK DIAGRAM
2
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7224 is a precision 8-bit voltage-output, digital-to-
analog converter, with output amplifier and double buffered
interface logic on a monolithic CMOS chip. No external trims
are required to achieve full specified performance for the part.
The double buffered interface logic consists of two 8-bit regis-
ters–an input register and a DAC register. Only the data held in
the DAC registers determines the analog output of the con-
verter. The double buffering allows simultaneous update in a
system containing multiple AD7224s. Both registers may be
made transparent under control of three external lines,
CS, WR
and
LDAC.
With both registers transparent, the
RESET
line
functions like a zero override; a useful function for system cali-
bration cycles. All logic inputs are TTL and CMOS (5 V) level
compatible and the control logic is speed compatible with most
8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. The part is also
specified for single supply operation using a reference of +10 V.
The output amplifier is capable of developing +10 V across a
2 kΩ load.
The AD7224 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC
2
MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
1. DAC and Amplifier on CMOS Chip
The single-chip design of the 8-bit DAC and output amplifier
is inherently more reliable than multi-chip designs. CMOS
fabrication means low power consumption (35 mW typical
with single supply).
2. Low Total Unadjusted Error
The fabrication of the AD7224 on Analog Devices Linear
Compatible CMOS (LC
2
MOS) process coupled with a novel
DAC switch-pair arrangement, enables an excellent total un-
adjusted error of less than 1 LSB over the full operating tem-
perature range.
3. Single or Dual Supply Operation
The voltage-mode configuration of the AD7224 allows opera-
tion from a single power supply rail. The part can also be op-
erated with dual supplies giving enhanced performance for
some parameters.
4. Versatile Interface Logic
The high speed logic allows direct interfacing to most micro-
processors. Additionally, the double buffered interface en-
ables simultaneous update of the AD7224 in multiple DAC
systems. The part also features a zero override function.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7224–SPECIFICATIONS
DUAL SUPPLY
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Temperature Coefficient
Zero Code Error
Zero Code Error Temperature Coefficient
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance
3
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
3
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
3
Voltage Output Settling Time
3
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Minimum Load Resistance
POWER SUPPLIES
V
DD
Range
V
SS
Range
I
DD
@ 25°C
T
MIN
to T
MAX
I
SS
@ 25°C
T
MIN
to T
MAX
SWITCHING CHARACTERISTICS
3, 4
t
1
@ 25°C
T
MIN
to T
MAX
t
2
@ 25°C
T
MIN
to T
MAX
t
3
@ 25°C
T
MIN
to T
MAX
t
4
@ 25°C
T
MIN
to T
MAX
t
5
@ 25°C
T
MIN
to T
MAX
t
6
@ 25°C
T
MIN
to T
MAX
(V
DD
= 11.4 V to 16.5 V, V
SS
= –5 V 10%; AGND = DGND = O V; V
REF
= +2 V to (V
DD
– 4 V)
1
unless otherwise noted.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
K, B, T
Versions
2
8
±
2
±
1
±
1
±
3/2
±
20
±
30
±
50
2 to (V
DD
– 4)
8
100
2.4
0.8
±
1
8
Binary
2.5
5
7
50
2
11.4/16.5
4.5/5.5
4
6
3
5
L, C, U
Versions
2
8
±
1
±
1/2
±
1
±
1
±
20
±
20
±
30
2 to (V
DD
– 4)
8
100
2.4
0.8
±
1
8
Binary
2.5
5
7
50
2
11.4/16.5
4.5/5.5
4
6
3
5
Units
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C max
mV max
µV/°C
typ
V min to V max
kΩ min
pF max
V min
V max
µA
max
pF max
Conditions/Comments
V
DD
= +15 V
±
5%, V
REF
= +10 V
Guaranteed Monotonic
V
DD
= 14 V to 16.5 V, V
REF
= +10 V
Occurs when DAC is loaded with all 1s.
V
IN
= 0 V or V
DD
V/µs min
µs
max
µs
max
nV secs typ
kΩ min
V min/V max
V min/V max
mA max
mA max
mA max
mA max
V
REF
= +10 V; Settling Time to
±
1/2 LSB
V
REF
= +10 V; Settling Time to
±
1/2 LSB
V
REF
= 0 V
V
OUT
= +10 V
For Specified Performance
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
Outputs Unloaded; V
IN
= V
INL
or V
INH
Outputs Unloaded; V
IN
= V
INL
or V
INH
Outputs Unloaded; V
IN
= V
INL
or V
INH
90
90
90
90
0
0
0
0
90
90
10
10
90
90
90
90
0
0
0
0
90
90
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Chip Select/Load DAC Pulse Width
Write/Reset Pulse Width
Chip Select/Load DAC to Write Setup Time
Chip Select/Load DAC to Write Hold Time
Data Valid to Write Setup Time
Data Valid to Write Hold Time
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C
3
Sample Tested at 25°C by Product Assurance to ensure compliance.
4
Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
–2–
REV. B
AD7224
SINGLE SUPPLY
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Differential Nonlinearity
REFERENCE INPUT
Input Resistance
Input Capacitance
3
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
3
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
Voltage Output Settling Time
4
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
3
Minimum Load Resistance
POWER SUPPLIES
V
DD
Range
I
DD
@ 25°C
T
MIN
to T
MAX
SWITCHING CHARACTERISTICS
3, 4
t
1
@ 25°C
T
MIN
to T
MAX
t
2
@ 25°C
T
MIN
to T
MAX
t
3
@ 25°C
T
MIN
to T
MAX
t
4
@ 25°C
T
MIN
to T
MAX
t
5
@ 25°C
T
MIN
to T
MAX
t
6
@ 25°C
T
MIN
to T
MAX
(V
DD
= +15 V 5%; V
SS
= AGND = DGND = O V; V
REF
= +10 V
1
unless otherwise noted.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
K, B, T
Versions
2
8
±
2
±
1
8
100
2.4
0.8
±
1
8
Binary
2
5
20
50
2
14.25/15.75
4
6
L, C, U
Versions
2
8
±
2
±
1
8
100
2.4
0.8
±
1
8
Binary
2
5
20
50
2
14.25/15.75
4
6
Units
Bits
LSB max
LSB max
kΩ min
pF max
V min
V max
µA
max
pF max
Conditions/Comments
Guaranteed Monotonic
Occurs when DAC is loaded with all 1s.
V
IN
= 0 V or V
DD
V/µs min
µs
max
µs
max
nV secs typ
kΩ min
V min/V max
mA max
mA max
Settling Time to
±
1/2 LSB
Settling Time to
±
1/2 LSB
V
REF
= 0 V
V
OUT
= +10 V
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
Outputs Unloaded; V
IN
= V
INL
or V
INH
90
90
90
90
0
0
0
0
90
90
10
10
90
90
90
90
0
0
0
0
90
90
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Chip Select/Load DAC Pulse Width
Write/Reset Pulse Width
Chip Select/Load DAC to Write Setup Time
Chip Select/Load DAC to Write Hold Time
Data Valid to Write Setup Time
Data Valid to Write Hold Time
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
AD7224KN, LN: 0°C to +70°C
AD7224BQ, CQ: –25°C to +85°C
AD7224TD, UD: –55°C to +125°C
3
See Terminology.
4
Sample tested at 25°C by Product Assurance to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
AD7224
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
OUT
to AGND
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
The outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 60 mA.
Model
1
AD7224KN
AD7224LN
AD7224KP
AD7224LP
AD7224KR-1
AD7224LR-1
AD7224KR-18
AD7224LR-18
AD7224BQ
AD7224CQ
AD7224TQ
AD7224UQ
AD7224TE
AD7224UE
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Total
Unadjusted
Error (LSB)
±
2 max
±
1 max
±
2 max
±
1 max
±
2 max
±
1 max
±
2 max
±
1 max
±
2 max
±
1 max
±
2 max
±
1 max
±
2 max
±
1 max
Package
Option
2
N-18
N-18
P-20A
P-20A
R-20
R-20
R-18
R-18
Q-18
Q-18
Q-18
Q-18
E-20A
E-20A
NOTES
1
To order MIL-STD-883 processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7224 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP and SOIC
V
SS
V
OUT
V
REF
AGND
DGND
(MSB) DB7
DB6
DB5
DB4
1
2
3
4
5
6
7
8
9
18
17
V
DD
RESET
V
SS
V
OUT
V
REF
AGND
DGND
(MSB) DB7
DB6
DB5
DB4
1
2
3
4
5
6
7
8
9
WARNING!
ESD SENSITIVE DEVICE
(SOIC)
18
17
V
DD
RESET
(SOIC)
V
SS
V
OUT
V
REF
AGND
DGND
(MSB) DB7
DB6
DB5
DB4
1
2
3
4
5
6
7
8
9
20
V
DD
19 RESET
18 LDAC
16 LDAC
16 LDAC
AD7224
15
WR
CS
DB0 (LSB)
AD7224
R-18
15
WR
CS
DB0 (LSB)
AD7224
R-20
17 WR
14
TOP VIEW
(Not to Scale)
13
14
TOP VIEW
(Not to Scale)
13
16 CS
TOP VIEW
(Not to Scale) 15 DB0 (LSB)
14 DB1
13 DB2
12 DB3
11 NC
12 DB1
11 DB2
10 DB3
12 DB1
11 DB2
10 DB3
NC 10
LCCC
RESET
V
OUT
V
OUT
V
SS
V
DD
PLCC
RESET
V
SS
NC
V
DD
NC = NO CONNECT
3
V
REF
4
AGND 5
DGND 6
(MSB) DB7 7
DB6 8
9
DB5
2
NC
1 20 19
18 LDAC
V
REF
AGND
DGND
(MSB) DB7
DB6
4
5
6
7
8
3
2
1
20 19
18 LDAC
AD7224
TOP VIEW
(Not to Scale)
17 WR
16 CS
15 DB0 (LSB)
14 DB1
AD7224
TOP VIEW
(Not to Scale)
17 WR
16 CS
15 DB0 (LSB)
14 DB1
10 11 12 13
DB4
DB3
DB2
NC
9
10 11 12 13
DB4
NC = NO CONNECT
NC = NO CONNECT
–4–
DB5
DB3
DB2
NC
REV. B
AD7224
TERMINOLOGY
TOTAL UNADJUSTED ERROR
V
OUT
=
D
•
V
REF
where
D
is a fractional representation of the digital input code
and can vary from 0 to 255/256.
OP-AMP SECTION
Total Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy and zero code error.
Maximum output voltage is V
REF
– 1 LSB (ideal), where 1 LSB
(ideal) is V
REF
/256. The LSB size will vary over the V
REF
range.
Hence the zero code error, relative to the LSB size, will increase
as V
REF
decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the V
REF
range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
RELATIVE ACCURACY
The voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. This buffer amplifier is
capable of developing +10 V across a 2 kΩ load and can drive
capacitive loads of 3300 pF.
The AD7224 can be operated single or dual supply resulting in
different performance in some parameters from the output am-
plifier. In single supply operation (V
SS
= 0 V = AGND) the sink
capability of the amplifier, which is normally 400
µA,
is reduced
as the output voltage nears AGND. The full sink capability of
400
µA
is maintained over the full output voltage range by tying
V
SS
to –5 V. This is indicated in Figure 2.
500
V
SS
= –5V
400
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
I
SINK
–
µA
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGH
300
V
SS
= 0V
200
V
DD
= +15V
T
A
= 25°C
Digital Feedthrough is the glitch impulse transferred to the out-
put due to a change in the digital input code. It is specified in
nV secs and is measured at V
REF
= 0 V.
FULL-SCALE ERROR
100
0
0
2
4
6
V
OUT
– Volts
8
10
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
Figure 2. Variation of I
SINK
with V
OUT
CIRCUIT INFORMATION
D/A SECTION
The AD7224 contains an 8-bit voltage-mode digital-to-analog
converter. The output voltage from the converter has the same
polarity as the reference voltage, allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7224 al-
lows a reference voltage range from +2 V to +12.5 V.
The DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS single pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in
Figure 1.
R
2R
V
REF
AGND
2R
DB0
R
2R
DB0
R
2R
DB0
2R
DB0
SHOWN FOR ALL 1's ON DAC
V
OUT
Settling-time for negative-going output signals approaching
AGND is similarly affected by V
SS
. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by V
SS
.
Additionally, the negative V
SS
gives more headroom to the out-
put amplifier which results in better zero code performance and
improved slew-rate at the output, than can be obtained in the
single supply mode.
DIGITAL SECTION
The AD7224 digital inputs are compatible with either TTL or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (V
DD
and DGND) as practi-
cally possible.
INTERFACE LOGIC INFORMATION
Figure 1. D/A Simplified Circuit Diagram
The input impedance at the V
REF
pin is code dependent and can
vary from 8 kΩ minimum to infinity. The lowest input imped-
ance occurs when the DAC is loaded with the digital code
01010101. Therefore, it is important that the reference presents
a low output impedance under changing load conditions. The
nodal capacitance at the reference terminals is also code depen-
dent and typically varies from 25 pF to 50 pF.
The V
OUT
pin can be considered as a digitally programmable
voltage source with an output voltage of:
REV. B
Table I shows the truth table for AD7224 operation. The part
contains two registers, an input register and a DAC register.
CS
and
WR
control the loading of the input register while
LDAC
and
WR
control the transfer of information from the input regis-
ter to the DAC register. Only the data held in the DAC register
will determine the analog output of the converter.
All control signals are level-triggered and therefore either or
both registers may be made transparent; the input register by
keeping
CS
and
WR
“LOW”, the DAC register by keeping
LDAC
and
WR
“LOW”. Input data is latched on the rising
edge of
WR.
–5–
Microcontroller MCU
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