K6T4016V3B, K6T4016U3B Family
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
0.1
History
Initial draft
Revise
- Die name change: A to B
Finalize
Revise
- Operating current update and release.
I
CC
(Read/Write) = 20/40
→
10/45mA
I
CC1
(Read/Write) = 20/40
→
10/45mA
I
CC2
= 90
→
70mA
Revise
- Change datasheet format
- Erase 70ns part from KM616V4000BI, KM616U4000B and
KM616U4000BI Family
- Power dissipation improved 0.7 to 1.0W
- V
IL
(MAX) improved 0.4 to 0.6V.
- I
CC2
decreased 70 to 60mA.
- Erase 100ns from KM616V4000B commercial product
Error correction
Revise
- Improved V
OH
(output high voltage) from 2.2V to 2.4V.
Draft Data
June 28, 1996
September 19, 1996
Remark
Advance
Preliminary
1.0
2.0
December 17, 1996
February 17, 1997
Final
Final
3.0
January 14, 1998
Final
3.01
3.02
August 7, 1998
October 15, 2001
Final
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.02
October 2001
K6T4016V3B, K6T4016U3B Family
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 256K x16
•
Power Supply Voltage
K6T4016V1B Family: 3.0~3.6V
K6T4016U1B Family: 2.7~3.3V
•
Low Data Retention Voltage: 2V(Min)
•
Three State Outputs
•
Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T4016V3B and K6T4016U3B families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fami-
lies support various operating temperature range and have
small package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
K6T4016V3B-B
K6T4016U3B-B
K6T4016V3B-F
K6T4016U3B-F
1. The parameter is measured with 30pF test load.
Operating Temperature
Vcc Range
3.0~3.6V
2.7~3.3V
Speed
Standby
(I
SB1
, Max)
15µA
Operating
(I
CC2
, Max)
PKG Type
Commercial(0~70°C)
70
1)
/85
1)
ns
85 /100ns
85
1)
/100ns
1)
60mA
20µA
44-TSOP2-400F/R
Industrial(-40~85°C)
3.0~3.6V
2.7~3.3V
PIN DESCRIPTION
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
A12
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
A13
A14
A0
A1
A15
A16
A17
A2
A3
A4
I/O
1
~I/O
8
Precharge circuit.
Vcc
Vss
44-TSOP2
Forward
44-TSOP2
Reverse
Row
select
Memory array
1024 rows
256×16 columns
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
I/O
9
~I/O
16
Name
CS
OE
WE
A
0
~A
17
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Name
LB
UB
Vcc
Vss
NC
Function
A8 A9 A10 A5 A6 A7 A4 A12
Lower Byte (I/O
1~8
)
Upper Byte(I/O
9~16
)
Power
Ground
No Connection
WE
OE
UB
LB
CS
I/O
1
~I/O
16
Data Inputs/Outputs
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
Revision 3.02
October 2001
2
K6T4016V3B, K6T4016U3B Family
PRODUCT LIST
Commercial Temperature Product(0~70°C)
Part Name
K6T4016V3B-TB70
K6T4016V3B-TB85
K6T4016V3B-RB70
K6T4016V3B-RB85
K6T4016U3B-TB85
K6T4016U3B-TB10
K6T4016U3B-RB85
K6T4016U3B-RB10
Function
44-TSOP2-F, 70ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-R, 70ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
Function
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-F, 100ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
44-TSOP2-R, 100ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL
K6T4016V3B-TF85
K6T4016V3B-TF10
K6T4016V3B-RF85
K6T4016V3B-RF10
K6T4016U3B-TF85
K6T4016U3B-TF10
K6T4016U3B-RF85
K6T4016U3B-RF10
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
L
L
L
L
L
OE
X
1)
H
X
1)
L
L
L
X
1)
X
1)
X
1)
WE
X
1)
H
X
1)
H
H
H
L
L
L
LB
X
1)
X
1)
H
L
H
L
L
H
L
UB
X
1)
X
1)
H
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
1. X means don′t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
260°C, 10sec (Lead Only)
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
Commercial
Industrial
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.02
October 2001
K6T4016V3B, K6T4016U3B Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
K6T4016V3B Family
K6T4016U3B Family
All Family
K6T4016V3B, K6T4016U3B Family
K6T4016V3B, K6T4016U3B Family
Min
3.0
2.7
0
2.2
-0.3
3)
Typ
3.3
3.0
0
-
-
CMOS SRAM
Max
3.6
3.3
0
Vcc+0.3
2)
0.6
Unit
V
V
V
V
Note:
1. Commercial Product: T
A
=0 to 70°C, otherwise specified
Industrial Product: T
A
=-40 to 85°C, otherwise specified
2. Overshoot: V
CC
+3.0V in case of pulse width
≤
30ns
3. Undershoot: -3.0V in case of pulse width
≤
30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
1. Industrial product = 20µA
Test Conditions
V
IL
=Vss to Vcc
CS=V
IH
or OE=V
IH
or WE=V
IL
V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA
CS≤0.2V, V
IN
≤0.2V
or V
IN
≥Vcc-0.2V
Read
Write
Min
-1
-1
-
-
-
-
-
2.4
-
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
1
1
10
10
45
60
0.4
-
0.5
15
1)
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
Average operating current
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
V
OL
V
OH
I
SB
I
SB1
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH,
Other inputs=V
IL
or V
IH
CS≥Vcc-0.2V, Others inputs = 0~Vcc
4
Revision 3.02
October 2001
K6T4016V3B, K6T4016U3B Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
C
L
1
)
1.Including scope and jig capacitance
AC CHARACTERISTICS
(K6T4016V3B Family: Vcc=3.0~3.6V, K6T4016U3B Family: Vcc=2.7~3.3V,
Commercial product: T
A=
0 to 70°C, Industrial product: T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
70ns
1)
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Read
Output enable to low-Z output
UB, LB enable to low-Z output
Chip disable to high-Z output
OE disable to high-Z output
Output hold from address change
LB, UB valid to data output
UB, LB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
1. The parameter is measured with 30pF test load
.
85ns
1)
Min
85
-
-
-
10
5
5
0
0
10
-
0
85
70
0
70
55
0
0
35
0
5
70
Max
-
85
85
40
-
-
-
25
25
-
40
25
-
-
-
-
-
-
25
-
-
-
-
-
100ns
Min
100
-
-
-
10
5
5
0
0
15
-
0
100
80
0
80
70
0
0
40
0
5
80
Max
-
100
100
50
-
-
-
30
30
-
50
30
-
-
-
-
-
-
30
-
-
-
-
Units
Max
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
OH
t
BA
t
BHZ
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
BW
70
-
-
-
10
5
5
0
0
10
-
0
70
60
0
60
55
0
0
30
0
5
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
35
-
-
-
25
25
-
35
25
-
-
-
-
-
-
25
-
-
-
-
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
1. Industrial product = 20µA
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS≥Vcc-0.2V
Vcc=3.0V, CS≥Vcc-0.2V
See data retention waveform
Min
2.0
-
0
5
Typ
-
0.5
-
-
Max
3.6
15
1)
-
-
Unit
V
µA
ms
5
Revision 3.02
October 2001
ARM Technology
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