DS2181A
CEPT Primary Rate Transceiver
www.dalsemi.com
FEATURES
Single chip primary rate transceiver meets
CCITT standards G.704, G.706 and G.732
Supports new CRC4-based framing
standards and CAS and CCS signaling
standards
Simple serial interface used for device
configuration and control in processor mode
Hardware mode requires no host processor;
intended for stand-alone applications
Comprehensive, on-chip alarm generation,
alarm detection, and error logging logic
Shares footprint with DS2180A T1
Transceiver
Comparison to DS2175 T1/CEPT Elastic
Store, DS2186 Transmit Line Interface,
DS2187 Receive Line Interface, and DS2188
Jitter Attenuator
5V supply; low-power CMOS technology
PIN ASSIGNMENT
TMSYNC
TFSYNC
TCLK
TCHCLK
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
INT
SDI
SDO
CS
SCLK
SPS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
RLOS
RFER
RBV
RCL
RNEG
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSER
RCHCLK
RCLK
RAF
RDMA
RRA
40-Pin DIP (600-mil)
RFSA
TCHCLK
TCLK
RMSA
TFSYNC
TMSYNC
VDD
RLOS
RFER
RBV
RCL
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
INT
SDI
5
4
3
2
1
44
43
42
41
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SDO
CS
SCLK
SPS
VSS
RRA
RDMA
RCTO
RAF
RCLK
RCSA
19
20
21
22
23
24
25
26
27
7
8
9
10
11
12
13
14
15
16
17
44-PIN PLCC
39
38
37
36
35
34
33
32
31
30
29
RNEG
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSER
RCHCLK
112099
DS2181A
DESCRIPTION
The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red
Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns and
CRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when
enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and CRC4
multiframe alignments. Once synchronized, the device extracts channel, signaling, and alarm data.
A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode,
a host processor controls features such as error logging, per-channel code manipulation, and alteration of
the receive synchronizer algorithm.
The hardware mode is intended for preliminary system prototyping and/or retrofitting into existing
systems. This mode requires no host processor and disables special features available in the processor
mode.
DS2180A BLOCK DIAGRAM
Figure 1
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DS2181A
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY)
Table 1
PIN
1
SYMBOL
TMSYNC
TYPE
I
DESCRIPTION
Transmit Multiframe Sync.
Low-high transition establishes start of
CAS and/or CRC4 multiframe. Can be tied low, allowing internal
multiframe counter to run free.
Transmit Frame Sync.
Low-high transition every frame period
establishes frame boundaries. Can be tied low, allowing TMSYNC to
establish frame boundaries.
Transmit Clock.
2.048 MHz primary clock.
Transmit Channel Clock.
256 kHz clock which identifies timeslot
boundaries. Useful for parallel-to-serial conversion of channel data.
Transmit Serial Data.
NRZ data input, sampled on falling edges of
TCLK.
Transmit Multiframe Out.
Output of multiframe counter; high
during frame 0, low otherwise.
Transmit Extra Data.
Sampled on falling edge of TCLK during bit
times 5, 7, and 8 of timeslot 16 in frame 0 when CAS signaling is
enabled.
Transmit Signaling Timeslot.
High during timeslot 16 of every
frame, low otherwise.
Transmit Signaling Data.
CAS signaling data input; sampled on
falling edges of TCLK for insertion into outgoing timeslot 16 when
enabled.
Transmit International and National Data.
Sampled on falling
edge of TCLK during bit 1 time of timeslot 0 every frame
(international) and/or during bit times 4 through 8 of timeslot 0 during
non-align frames (national) when enabled.
Transmit Alignment Frame.
High during frames containing the
frame alignment signal, low otherwise.
Transmit Bipolar Data Outputs.
Updated on rising edge of TCLK.
2
TFSYNC
I
3
4
5
6
7
TCLK
TCHCLK
TSER
TMO
TXD
I
O
I
O
I
8
9
TSTS
TSD
O
I
10
TIND
I
11
12
13
TAF
TPOS
TNEG
O
O
SYCHRONIZER STATUS PIN (44-PIN PLCC ONLY)
Table 2A
PIN
3
SYMBOL
RMSA
TYPE
O
DESCRIPTION
Receive Multiframe Search Active.
This pin will transition high
when the synchronizer searching for the CAS multiframe alignment
word is active.
Receive Frame Search Active.
This pin will transition high when the
synchronizer searching for the FAS is active.
Receive CRC4 Time Out.
This pin will transition high when the
RCTO counter reaches its maximum count of 32. The pin will return
low when either the DS2181AQ reaches CRC4 multiframe
synchronization, or if CRC4 is disabled via CRC.2, or if the device is
issued a hardware reset via the
RST
pin.
Receive CRC4 Search Active.
This pin will transition high when the
synchronizer searching for the CRC4 multiframe alignment word is
active.
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6
25
RFSA
RCTO
O
O
28
RCSA
O
DS2181A
NOTES:
1. These output status pins are only available on the DS2181AQ.
2. If the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY)
Table 2B
PIN
21
22
23
24
25
26
27
28
29
30
31
SYMBOL
RRA
RMDA
RAF
RCLK
RCHCLK
RSER
RFSYNC
RMSYNC
RSD
RSTS
RCSYNC
TYPE
O
O
O
I
O
O
O
O
O
O
O
DESCRIPTION
Receive Remote Alarm.
Transitions high when alarm detected;
returns low when alarm cleared.
Receive Distant Multiframe Alarm.
Transitions high when alarm
detected; returns low when alarm cleared.
Receive Alignment Frame.
High during frames containing the frame
alignment signal, low otherwise.
Receive Clock.
2.048 MHz primary clock.
Receive Channel Clock.
256 kHz clock, identifies timeslot
boundaries; useful for serial-to-parallel conversion of channel data.
Receive Channel Clock.
256 kHz clock, identifies timeslot
boundaries; useful for serial-to-parallel conversion of channel data.
Receive Frame Sync.
Trailing edge indicates start of frame.
Receive Multiframe Sync.
Low-high transition indicates start of
CAS multiframe; held high during frame 0.
Receive Signaling Data.
Extracted timeslot 16 data; updated on
rising edge of RCLK.
Receive Signaling Timeslot.
High during timeslot 16 of every frame,
low otherwise.
Receive CRC4 Sync.
Low-high transition indicates start of CRC4
multiframe; held high during CRC4 frames 0 through 7 and held low
during frames 8 through 15.
Reset.
Must be asserted during device power-up and when changing
to/from the hardware mode.
Receive Bipolar Data.
Sampled on falling edges of RCLK. Tie
together to receive NRZ data and disable BPV monitor circuitry.
Receive Carrier Loss.
Low-high transition indicates loss of carrier.
Receive Bipolar Violation.
Pulses high during detected bipolar
violations.
Receive Frame Error.
Pulses high when frame alignment, CAS
multiframe alignment or CRC4 words received in error.
Receive Loss of Sync.
Indicates synchronizer status; high when
frame, CAS and/or CRC4 multiframe search underway, low
otherwise.
33
34
35
36
37
38
39
RST
I
I
O
O
O
O
RPOS
RNEG
RCL
RBV
RFER
RLOS
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DS2181A
PORT PIN DESCRIPTION (40-PIN DIP ONLY)
Table 3
PIN
14
15
16
SYMBOL
INT
TYPE
O
I
O
SDI
SDO
17
18
19
CS
I
I
I
DESCRIPTION
Receive Alarm Interrupt.
Flags host controller during alarm
conditions. Active low; open drain output.
Serial Data In.
Data for on-chip control registers; sampled on rising
edge of SCLK.
Serial Data Out.
Control and status data from on-chip registers.
Updated on falling edge of SCLK; tri-stated during port write or when
CS
is high.
Chip Select.
Must be low to write or read the serial port.
Serial Data Clock.
Used to write or read the serial port registers.
Serial
Port Select.
Tie to V
DD
to select the serial port. Tie to V
SS
to
select the hardware mode.
SCLK
SPS
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY)
Table 4
PIN
20
32
SYMBOL
V
SS
TEST
TYPE
-
I
DESCRIPTION
Signal Ground.
0.0 volts.
Test Mode.
Tie to V
SS
to select the old DS2181 sync algorithm and to
tri–state the synchronizer status pins on the DS2181AQ. Tie to V
DD
to select the new DS2181A sync algorithm and activate the
synchronizer status pins on the DS2181AQ.
Positive Supply.
5.0 volts.
40
V
DD
-
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