5V60014DVGI datasheet, PDF - EEWORLD Datasheet

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5V60014DVGI: DescriptionPLL Based Clock Driver, 5V Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 3 MM, ROHS COMPLIANT, MSOP-8; Categorylogic; File Size178KB，8 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5V60014DVGI Overview

PLL Based Clock Driver, 5V Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 3 MM, ROHS COMPLIANT, MSOP-8

5V60014DVGI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	MSOP
package instruction	3 MM, ROHS COMPLIANT, MSOP-8
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Is Samacsys	N
series	5V
Input adjustment	STANDARD
JESD-30 code	S-PDSO-G8
JESD-609 code	e3
length	3 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.025 A
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP8,.19
Package shape	SQUARE
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
Base Number Matches	1

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DATASHEET

LOW PHASE NOISE ZERO DELAY BUFFER

Description

The IDT5V60014 is a high speed, high output drive, low

phase noise Zero Delay Buffer (ZDB) which integrates IDT’s

proprietary analog/digital Phase Locked Loop (PLL)

techniques. The IDT5V60014 is designed to operate at low

frequencies, with faster rise and fall times, and with lower

phase noise. The zero delay feature means that the rising

edge of the input clock aligns with the rising edges of both

outputs, giving the appearance of no delay through the

device. There are two outputs on the chip. The device has

internal feedback loop eliminating the complexity of external

feedback loop.

The chip is ideal for synchronizing outputs in a large variety

of systems, from personal computers to data

communications to video. The low phase noise

performance makes the device particularly suitable for

audio applications. By allowing off-chip feedback paths, the

IDT5V60014 can eliminate the delay through other devices.

IDT5V60014

Features

•

Packaged in 8-pin MSOP (Pb free)

Low phase noise zero delay buffer

Low skew outputs

Input clock frequency from 10 MHz to 38 MHz at 3.3 V

Phase noise of better than -100 dBc/Hz from 1 kHz to

1 MHz offset from carrier

Recover poor input clock duty cycle

Output clock duty cycle of 45/55 at 3.3 V

High drive strength

Full CMOS clock swings with 15 mA drive capability at

TTL levels

•

Advanced, low power CMOS process

•

3.3 V operating voltages

•

Industrial Temperature Range: -40 to +85° C

Block Diagram

ICLK

Phase

Detector,

Charge

pump, and

Loop Filter

VCO

Output

Buffer

CLK1

Output

Buffer

CLK2

Internal feedback

IDT™

LOW PHASE NOISE ZERO DELAY BUFFER

IDT5V60014

REV D 040609

5V60014DVGI Related Products

	5V60014DVGI	5V60014DVGI8
Description	PLL Based Clock Driver, 5V Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 3 MM, ROHS COMPLIANT, MSOP-8	PLL Based Clock Driver, 5V Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 3 MM, ROHS COMPLIANT, MSOP-8
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	MSOP	MSOP
package instruction	3 MM, ROHS COMPLIANT, MSOP-8	3 MM, ROHS COMPLIANT, MSOP-8
Contacts	8	8
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
series	5V	5V
Input adjustment	STANDARD	STANDARD
JESD-30 code	S-PDSO-G8	S-PDSO-G8
JESD-609 code	e3	e3
length	3 mm	3 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.025 A	0.025 A
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	8	8
Actual output times	2	2
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP8,.19	TSSOP8,.19
Package shape	SQUARE	SQUARE
Package form	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	3 mm	3 mm
Base Number Matches	1	1

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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