NCP163
250 mA, Ultra-Low Noise
and High PSRR LDO
Regulator for RF and
Analog Circuits
The NCP163 is a next generation of high PSRR, ultra−low noise
LDO capable of supplying 250 mA output current. Designed to meet
the requirements of RF and sensitive analog circuits, the NCP163
device provides ultra−low noise, high PSRR and low quiescent
current. The device also offer excelent load/line transients. The
NCP163 is designed to work with a 1
mF
input and a 1
mF
output
ceramic capacitor. It is available in two thickness ultra−small 0.35P,
WLCSP Packages, XDFN4 0.65P and industry standard SOT23−5L.
Features
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MARKING
DIAGRAMS
WLCSP4
CASE 567JZ
X
A1
•
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 2.2 V to 5.5 V
Available in Fixed Voltage Option: 1.2 V to 5.3 V
±2%
Accuracy Over Load/Temperature
Ultra Low Quiescent Current Typ. 12
mA
Standby Current: Typ. 0.1
mA
Very Low Dropout: 80 mV at 250 mA
Ultra High PSRR: Typ. 92 dB at 20 mA, f = 1 kHz
Ultra Low Noise: 6.5
mV
RMS
Stable with a 1
mF
Small Case Size Ceramic Capacitors
Available in
−
WLCSP4: 0.65 mm x 0.65 mm x 0.33 mm
−
WLCSP4: 0.65 mm x 0.65 mm x 0.4 mm
−
XDFN4: 1 mm x 1 mm x 0.4 mm
−
SOT23−5: 2.9 mm x 2.8 mm x 1.2 mm
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
WLCSP4
CASE 567KA
A1
X
1
XDFN4
CASE 711AJ
XX M
1
SOT23−5L
CASE 527AH
XXX MG
G
X, XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
IN
A1
B1
OUT
A2
B2
•
•
•
•
Battery−powered Equipment
Wireless LAN Devices
Smartphones, Tablets
Cameras, DVRs, STB and Camcorders
V
OUT
IN
NCP163
C
IN
1
mF
Ceramic
EN
ON
OFF
GND
C
OUT
1
mF
Ceramic
OUT
V
IN
EN
GND
(Top View)
(Top View)
IN
GND
EN
1
2
3
(Top View)
5
OUT
4
NC
Figure 1. Typical Application Schematics
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 17 of this data sheet.
©
Semiconductor Components Industries, LLC, 2016
November, 2018
−
Rev. 9
1
Publication Order Number:
NCP163/D
NCP163
IN
EN
BANDGAP
REFERENCE
MOSFET
INTEGRATED
SOFT−START
DRIVER WITH
CURRENT LIMIT
ENABLE
LOGIC
THERMAL
SHUTDOWN
OUT
* ACTIVE DISCHARGE
Version A only
EN
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
WLCSP4
A1
A2
B1
B2
−
−
Pin No.
SOT23−5L
1
5
3
2
4
−
Pin No.
XDFN4
4
1
3
2
−
EPAD
Pin
Name
IN
OUT
EN
GND
NC
EPAD
Input voltage supply pin
Regulated output voltage. The output should be bypassed with small 1
mF
ceramic
capacitor.
Chip enable: Applying V
EN
< 0.4 V disables the regulator, Pulling V
EN
> 1.2 V
enables the LDO.
Common ground connection
Not connected. Can be tied to ground plane.
Exposed pad. Can be tied to ground plane for better power dissipation.
Description
ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage (Note 1)
Output Voltage
Chip Enable Input
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Symbol
V
IN
V
OUT
V
CE
t
SC
T
J
T
STG
ESD
HBM
ESD
MM
ESD
CDM
Value
−0.3
V to
6
−0.3
to V
IN
+ 0.3, max. 6 V
−0.3
to 6 V
unlimited
150
−55
to 150
2000
200
1000
Unit
V
V
V
s
°C
°C
V
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
ESD Charged Device Model tested per EIA/JESD22−C101, Field Induced Charge Model
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
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NCP163
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, WLCSP4 (Note 3), Thermal Resistance, Junction−to−Air
Thermal Characteristics, XDFN4 (Note 3), Thermal Resistance, Junction−to−Air
Thermal Characteristics, SOT23−5 (Note 3), Thermal Resistance, Junction−to−Air
R
qJA
Symbol
Value
108
198.1
218
°C/W
Unit
3. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD51−7
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
J
≤
125°C; V
IN
= V
OUT(NOM)
+ 1 V; I
OUT
= 1 mA, C
IN
= C
OUT
= 1
mF,
unless otherwise
noted. V
EN
= 1.2 V. Typical values are at T
J
= +25°C (Note 4).
Parameter
Operating Input Voltage
Output Voltage Accuracy
V
IN
= (V
OUT(NOM)
+ 1 V) to 5.5 V
0 mA
≤
I
OUT
≤
250 mA
V
IN
= (V
OUT(NOM)
+ 1 V) to 5.5 V
0 mA
≤
I
OUT
≤
250 mA
(for V
OUT
< 1.8 V, XDFN4 package)
V
IN
= (V
OUT(NOM)
+ 1 V) to 5.5 V
SOT23−5L Package Only
Line Regulation
Load Regulation
V
OUT(NOM)
+ 1 V
≤
V
IN
≤
5.5 V
I
OUT
= 1mA to 250mA
WLCSP, XDFN4
SOT23−5L
V
OUT(NOM)
= 1.8 V
V
OUT(NOM)
= 2.5 V
V
OUT(NOM)
= 2.8 V
I
OUT
= 250 mA
(WLCSP, XDFN4
Packages)
V
OUT(NOM)
= 3.0 V
V
OUT(NOM)
= 3.2 V
V
OUT(NOM)
= 3.3 V
V
OUT(NOM)
= 3.5 V
V
OUT(NOM)
= 4.5 V
V
OUT(NOM)
= 5.0 V
V
OUT(NOM)
= 1.8 V
Dropout Voltage (Note 5)
I
OUT
= 250 mA
(SOT23−5L
Package)
V
OUT(NOM)
= 2.8 V
V
OUT(NOM)
= 3.0 V
V
OUT(NOM)
= 3.3 V
Output Current Limit
Short Circuit Current
Quiescent Current
Shutdown Current
EN Pin Threshold Voltage
V
OUT
= 90% V
OUT(NOM)
V
OUT
= 0 V
I
OUT
= 0 mA
V
EN
≤
0.4 V, V
IN
= 4.8 V
EN Input Voltage “H”
EN Input Voltage “L”
EN Pull Down Current
Turn−On Time
Power Supply Rejection Ratio
V
EN
= 4.8 V
C
OUT
= 1
mF,
From assertion of V
EN
to
V
OUT
= 95% V
OUT(NOM)
I
OUT
= 20 mA
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 kHz
PSRR
I
CL
I
SC
I
Q
I
DIS
V
ENH
V
ENL
I
EN
0.2
120
91
92
85
60
1.2
0.4
0.5
250
V
DO
V
DO
Line
Reg
Load
Reg
V
OUT
Test Conditions
Symbol
V
IN
Min
2.2
−2
−3
−2
0.02
0.001
0.008
180
110
95
90
85
80
75
65
75
205
120
115
105
700
690
12
0.01
20
1
0.015
250
175
160
155
149
145
140
120
105
280
190
185
175
mA
mA
mA
V
mA
ms
mV
mV
Typ
Max
5.5
+2
+3
+2
%/V
%/mA
%
Unit
V
Dropout Voltage (Note 5)
dB
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NCP163
ELECTRICAL CHARACTERISTICS
−40°C
≤
T
J
≤
125°C; V
IN
= V
OUT(NOM)
+ 1 V; I
OUT
= 1 mA, C
IN
= C
OUT
= 1
mF,
unless otherwise
noted. V
EN
= 1.2 V. Typical values are at T
J
= +25°C (Note 4).
Parameter
Output Voltage Noise
Thermal Shutdown Threshold
Test Conditions
f = 10 Hz to 100 kHz
I
OUT
= 1 mA
I
OUT
= 250 mA
Symbol
V
N
T
SDH
T
SDL
R
DIS
−1
Tran
LINE
+1
Tran
LOAD
−40
+40
mV
mV
Min
Typ
8.0
6.5
160
140
280
Max
Unit
mV
RMS
°C
°C
W
Temperature rising
Temperature falling
Active Output Discharge Resistance
Line Transient (Note 6)
V
EN
< 0.4 V, Version A only
V
IN
= (V
OUT(NOM)
+ 1 V) to (V
OUT(NOM)
+
1.6 V) in 30
ms,
I
OUT
= 1 mA
V
IN
= (V
OUT(NOM)
+ 1.6 V) to (V
OUT(NOM)
+
1 V) in 30
ms,
I
OUT
= 1 mA
Load Transient (Note 6)
I
OUT
= 1 mA to 200 mA in 10
ms
I
OUT
= 200 mA to 1mA in 10
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T
A
= 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when V
OUT
falls 100 mV below V
OUT(NOM)
.
6. Guaranteed by design.
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NCP163
TYPICAL CHARACTERISTICS
1.830
1.825
V
OUT
, OUTPUT VOLTAGE (V)
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
−40 −20
0
20
40
60
80
I
OUT
= 10 mA
V
OUT
, OUTPUT VOLTAGE (V)
3.335
3.330
3.325
3.320
3.315
3.310
3.305
3.300
3.295
3.290
3.285
−40 −20
V
IN
= 4.3 V
V
OUT
= 3.3 V
C
IN
= 1
mF
C
OUT
= 1
mF
0
20
40
60
80
100
120 140
I
OUT
= 250 mA
I
OUT
= 10 mA
I
OUT
= 250 mA
V
IN
= 2.8 V
V
OUT
= 1.8 V
C
IN
= 1
mF
C
OUT
= 1
mF
100
120
140
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 3. Output Voltage vs. Temperature
−
V
OUT
= 1.8 V
−
XDFN Package
5.040
REG
LINE
, LINE REGULATION (%/V)
V
OUT
, OUTPUT VOLTAGE (V)
5.035
5.030
5.025
5.020
5.015
5.010
5.005
5.000
4.995
4.990
−40 −20
0
20
40
60
80
I
OUT
= 250 mA
V
IN
= 5.5 V
V
OUT
= 5.0 V
C
IN
= 1
mF
C
OUT
= 1
mF
100
120
I
OUT
= 10 mA
0.05
0.04
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
Figure 4. Output Voltage vs. Temperature
−
V
OUT
= 3.3 V
−
XDFN Package
V
IN
= 2.8 V
V
OUT
= 1.8 V
C
IN
= 1
mF
C
OUT
= 1
mF
0
20
40
60
80
100
120 140
140
−0.05
−40 −20
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage vs. Temperature
−
V
OUT
= 5.0 V
−
XDFN Package
Figure 6. Line Regulation vs. Temperature
−
V
OUT
= 1.8 V
REG
LOAD
, LOAD REGULATION (mV)
0.050
REG
LINE
, LINE REGULATION (%/V)
0.040
0.030
0.020
0.010
0
20
18
16
14
12
10
8
6
4
2
0
−40 −20
0
20
40
60
80
100
120 140
V
IN
= 2.8 V
V
OUT
= 1.8 V
C
IN
= 1
mF
C
OUT
= 1
mF
−0.010
−0.020
−0.030
−0.040
V
IN
= 4.3 V
V
OUT
= 3.3 V
C
IN
= 1
mF
C
OUT
= 1
mF
0
20
40
60
80
100
120
140
−0.050
−40 −20
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 7. Line Regulation vs. Temperature
−
V
OUT
= 3.3 V
Figure 8. Load Regulation vs. Temperature
−
V
OUT
= 1.8 V
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