CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
W, U versions respectively
-20
V
CC
= 3.3V @ 25°C
Wiper current = V
CC
/R
TOTAL
70
10/10/25
Voltage at pin from GND to V
CC
0.1
1
MIN
TYP
(Note 1)
10, 50
+20
200
MAX
UNIT
k
%
pF
µA
PARAMETER
R
H
to R
L
Resistance
R
H
to R
L
Resistance Tolerance
R
W
C
H
/C
L
/C
W
I
LkgDCP
Wiper Resistance
Potentiometer Capacitance (Note 15)
Leakage on DCP Pins (Note 15)
VOLTAGE DIVIDER MODE
(0V @ RL
i
; V
CC
@ RH
i
; measured at RW
i
, unloaded; i = 0, 1, 2, or 3)
INL (Note 6)
Integral Non-linearity
Monotonic over all tap positions
U option
W option
Full-scale Error
U option
W option
DCP to DCP Matching
Any two DCPs at same tap position, same
voltage at all RH terminals, and same voltage
at all RL terminals
DCP Register set to 80 hex
-1
-0.5
0
0
-7
-2
-2
1
0.5
-1
-1
1
0.5
7
2
0
0
2
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
DNL (Note 5) Differential Non-linearity
ZSerror
(Note 3)
FSerror
(Note 4)
V
MATCH
(Note 7)
Zero-scale Error
TC
V
(Note 8) Ratiometric Temperature Coefficient
±4
RESISTOR MODE
(Measurements between RW
i
and RL
i
with RH
i
not connected, or between RW
i
and RH
i
with RL
i
not connected. i = 0, 1, 2 or 3)
RINL
(Note 12)
RDNL
(Note 11)
Roffset
(Note 10)
Integral Non-linearity
Differential Non-linearity
Offset
U option
W option
R
MATCH
(Note 13)
TC
R
(Note 14)
DCP to DCP Matching
Resistance Temperature Coefficient
Any two DCPs at the same tap position with
the same terminal voltages.
DCP register set between 20 hex and FF hex
DCP register set between 20 hex and
FF hex. Monotonic over all tap positions
-1
-0.5
0
0
-2
±45
1
0.5
1
0.5
7
2
2
MI
(Note 9)
MI
(Note 9)
MI
(Note 9)
MI
(Note 9)
MI
(Note 9)
ppm/°C
FN8213 Rev 2.00
July 5, 2006
Page 3 of 13
X95840
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
CC2
I
SB
PARAMETER
V
CC
Supply Current
(Volatile write/read)
V
CC
Supply Current
(nonvolatile write)
V
CC
Current (standby)
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for
I
2
C
,
Active, Read and Volatile Write States only)
f
SCL
= 400kHz; SDA = Open; (for
I
2
C
,
Active, Nonvolatile Write State only)
V
CC
= +5.5V,
I
2
C
Interface in Standby State
V
CC
= +3.6V,
I
2
C
Interface in Standby State
I
LkgDig
Leakage Current, at
Pins A0, A1, A2, SDA, SCL,
and WP Pins
DCP Wiper Response Time
Power-on Recall Voltage
V
CC
Ramp Rate
Power-up Delay
V
CC
above Vpor, to DCP Initial Value Register recall
completed, and
I
2
C
Interface in standby state
Voltage at pin from GND to V
CC
-10
MIN
TYP
(Note 1)
MAX
1
3
5
2
10
UNITS
mA
mA
µA
µA
µA
t
DCP
(Note 15)
Vpor
VccRamp
t
D
(Note 15)
SCL falling edge of last bit of DCP Data Byte to wiper
change
Minimum V
CC
at which memory recall occurs
1.8
0.2
1
2.6
µs
V
V/ms
3
ms
EEPROM SPECS
EEPROM Endurance
EEPROM Retention
SERIAL INTERFACE SPECS
V
IL
WP, A2, A1, A0, SDA, and
SCL Input Buffer LOW
Voltage
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer
Hysteresis
-0.3
0.3*V
CC
V
Temperature
75°C
150,000
50
Cycles
Years
V
IH
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 15)
0.05*
V
CC
0
0.4
10
400
50
900
1300
V
V
pF
kHz
ns
ns
ns
V
OL
(Note 15) SDA outPut Buffer LOW
Voltage, Sinking 4mA
Cpin
(Note 15)
f
SCL
t
IN
(Note 15)
WP, A2, A1, A0, SDA, and
SCL Pin Capacitance
SCL frEquency
Pulse Width Suppression
Any pulse narrower than the max spec is suppressed.
Time at SDA and SCL Inputs
SCL falling edge crossing 30% of V
CC
, until SDA exits
the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP condition, to
SDA crossing 70% of V
CC
during the following START
condition.
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both crossing
70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to SCL
falling edge crossing 70% of V
CC
.
t
AA
(Note 15) SCL Falling Edge to SDA
Output Data Valid
t
BUF
(Note 15)
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup
Time
START Condition Hold Time
1300
600
600
600
ns
ns
ns
ns
FN8213 Rev 2.00
July 5, 2006
Page 4 of 13
X95840
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STO
PARAMETER
Input Data Setup Time
Input Data Hold Time
TEST CONDITIONS
From SDA exiting the 30% to 70% of V
CC
window, to
SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to SDA
entering the 30% to 70% of V
CC
window.
MIN
100
0
600
600
0
20 +
0.1 * Cb
20 +
0.1 * Cb
10
1
250
250
400
TYP
(Note 1)
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
pF
k
STOP Condition Setup Time From SCL rising edge crossing 70% of V
CC
, to SDA
rising edge crossing 30% of V
CC
.
STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both
京公网安备 11010802033920号
EEWORLD
