HUFA76432P3, HUFA76432S3S
Data Sheet
December 2001
55A, 60V, 0.019 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFETs
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
JEDEC TO-263AB
DRAIN
(FLANGE)
Features
• Ultra Low On-Resistance
- r
DS(ON)
= 0.017Ω,
V
GS
=
10V
- r
DS(ON)
= 0.019Ω,
V
GS
=
5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
HUFA76432P3
HUFA76432S3S
Symbol
D
• Switching Time vs R
GS
Curves
Ordering Information
PART NUMBER
PACKAGE
TO-220AB
TO-263AB
BRAND
76432P
76432S
HUFA76432P3
G
S
HUFA76432S3S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUFA76432S3ST.
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUFA76432P3, HUFA76432S3S
UNITS
V
V
V
A
A
A
A
60
60
±16
55
59
39
37
Figure 4
Figures 6, 17, 18
130
0.87
-55 to 175
300
260
W
mW/
o
C
o
C
o
C
o
C
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
NOTES:
1. T
J
= 25
o
C to 150
o
C.
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA76432P3, HUFA76432S3S Rev. B
HUFA76432P3, HUFA76432S3S
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
DSS
I
GSS
V
GS(TH)
r
DS(ON)
I
D
= 250µA, V
GS
= 0V (Figure 12)
I
D
= 250µA, V
GS
= 0V , T
C
= -40
o
C (Figure 12)
Zero Gate Voltage Drain Current
V
DS
= 55V, V
GS
= 0V
V
DS
= 50V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
GS
= V
DS
, I
D
= 250µA (Figure 11)
I
D
= 59A, V
GS
= 10V (Figures 9, 10)
I
D
= 39A, V
GS
= 5V (Figure 9)
I
D
= 37A, V
GS
= 4.5V (Figure 9)
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
R
θJC
R
θJA
TO-220AB and TO-263AB
-
-
-
-
1.15
62
o
C/W
o
C/W
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
60
55
-
-
-
-
-
-
-
-
-
-
1
250
±100
V
V
µA
µA
nA
V
GS
=
±16V
1
-
-
-
-
0.014
0.016
0.017
3
0.017
0.019
0.021
V
Ω
Ω
Ω
SWITCHING SPECIFICATIONS
(V
GS
= 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(5)
Q
g(TH)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 13)
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
GS
= 0V to 1V
V
DD
= 30V,
I
D
= 39A,
I
g(REF)
= 1.0mA
(Figures 14, 19, 20)
V
DD
= 30V, I
D
= 60A
V
GS
=
10V, R
GS
= 6.8Ω
(Figures 16, 21, 22)
V
DD
= 30V, I
D
= 37A
V
GS
=
4.5V, R
GS
= 6.2Ω
(Figures 15, 21, 22)
-
-
-
-
-
-
-
14
250
26
82
-
400
-
-
-
-
160
ns
ns
ns
ns
ns
ns
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Reverse Transfer Capacitance
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
-
-
-
1765
470
75
-
-
-
pF
pF
pF
-
-
-
-
-
44
24
1.6
4.3
9.8
53
29
2
-
-
nC
nC
nC
nC
nC
-
-
-
-
-
-
-
9.0
100
53
107
-
165
-
-
-
-
240
ns
ns
ns
ns
ns
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 39A
I
SD
= 20A
Reverse Recovery Time
Reverse Recovered Charge
I
SD
= 39A, dI
SD
/dt = 100A/µs
I
SD
= 39A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.00
65
120
UNITS
V
V
ns
nC
©2001 Fairchild Semiconductor Corporation
HUFA76432P3, HUFA76432S3S Rev. B
HUFA76432P3, HUFA76432S3S
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
70
60
I
D
, DRAIN CURRENT (A)
V
GS
= 10V
50
40
30
V
GS
= 4.5V
20
10
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
10
0
10
1
SINGLE PULSE
0.01
10
-5
10
-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
700
T
C
= 25
o
C
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
I = I
25
175 - T
C
150
I
DM
, PEAK CURRENT (A)
100
V
GS
= 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
40
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA76432P3, HUFA76432S3S Rev. B
HUFA76432P3, HUFA76432S3S
Typical Performance Curves
400
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
o
C
100
100µs
(Continued)
200
I
AS
, AVALANCHE CURRENT (A)
STARTING T
J
= 25
o
C
I
D
, DRAIN CURRENT (A)
100
10
STARTING T
J
= 150
o
C
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
10
0.001
0.01
0.1
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1ms
10ms
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
60
50
I
D,
DRAIN CURRENT (A)
40
30
20
10
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
I
D
, DRAIN CURRENT (A)
60
50
40
30
20
10
0
V
GS
= 10V
V
GS
= 5V
V
GS
= 4V
V
GS
= 3.5V
T
J
= 175
o
C
T
J
= -55
o
C
T
J
= 25
o
C
V
GS
= 3V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1
2
3
4
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
5
1.5
2
2.5
3
3.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
4
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
50
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
I
D
= 55A
r
DS(ON)
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
40
I
D
= 37A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
V
GS
= 10V, I
D
= 59A
30
I
D
= 18A
20
1.5
1.0
10
2
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
10
0.5
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
200
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA76432P3, HUFA76432S3S Rev. B
HUFA76432P3, HUFA76432S3S
Typical Performance Curves
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
(Continued)
1.2
I
D
= 250µA
1.0
1.1
0.8
1.0
0.6
0.4
-80
0.9
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4000
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
C
ISS
=
C
GS
+ C
GD
V
DD
= 30V
8
C, CAPACITANCE (pF)
1000
6
C
OSS
≅
C
DS
+ C
GD
4
100
V
GS
= 0V, f = 1MHz
30
0.1
1.0
10
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
RSS
=
C
GD
2
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 55A
I
D
= 37A
I
D
= 18A
0
10
20
30
40
50
0
Q
g
, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
750
V
GS
= 4.5V, V
DD
= 30V, I
D
= 37A
SWITCHING TIME (ns)
SWITCHING TIME (ns)
300
V
GS
= 10V, V
DD
= 30V, I
D
= 59A
500
t
r
200
t
f
100
t
d(OFF)
t
d(ON)
t
r
250
t
f
t
d(OFF)
t
d(ON)
0
0
10
20
30
40
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
50
0
0
10
20
30
40
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
HUFA76432P3, HUFA76432S3S Rev. B
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