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71V321L55PFI8

Description
IC SRAM 16K PARALLEL 64TQFP
Categorystorage   
File Size139KB,15 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

71V321L55PFI8 Overview

IC SRAM 16K PARALLEL 64TQFP

71V321L55PFI8 Parametric

Parameter NameAttribute value
memory typeVolatile
memory formatSRAM
technologySRAM - dual port, asynchronous
storage16Kb (2K x 8)
Write cycle time - words, pages55ns
interview time55ns
memory interfacein parallel
Voltage - Power3 V ~ 3.6 V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount
Package/casing64-LQFP
Supplier device packaging64-TQFP(14x14)
HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH
INTERRUPTS
Features
IDT71V321S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed access
– Commercial & Industrial: 25/35/55ns (max.)
Low-power operation
– IDT71V321S
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT71V321L
Active: 325mW (typ.)
Standby: 1mW (typ.)
Two
INT
flags for port-to-port communications
On-chip port arbitration logic (IDT71V321 only)
BUSY
output flag
Fully asynchronous operation from either port
Battery backup operation—2V data retention (L only)
TTL-compatible, single 3.3V power supply
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
A
10R
A
0R
(1,2)
A
10L
A
0L
Address
Decoder
11
MEMORY
ARRAY
11
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
3026 drw 01
(2)
NOTES:
1. IDT71V321 (MASTER):
BUSY
is an output
2.
BUSY
and
INT
are totem-pole outputs.
JANUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-3026/13
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