AT91SAM ARM-based Embedded MPU
SAM9263
Description
The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is archi-
tectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It
also features two independent external memory buses, EBI0 and EBI1, capable of interfac-
ing with a wide range of memory devices and an IDE hard disk. Two external buses prevent
bottlenecks, thus guaranteeing maximum performance.
The AT91SAM9263 embeds an LCD Controller supported by a Two D Graphics Controller
and a 2-channel DMA Controller, and one Image Sensor Interface. It also integrates several
standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multi-
media Card interface and one CAN Controller.
When coupled with an external GPS engine, the AT91SAM9263 provides the ideal solution
for navigation systems.
This is a summary document.
The complete document is
available on the Atmel website
at www.atmel.com.
6249IS–ATARM–28-Jan-13
1. Features
•
Incorporates the ARM926EJ-S
™
ARM
®
Thumb
®
Processor
– DSP Instruction Extensions, Jazelle
®
Technology for Java
®
Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICE
™
, Debug Communication Channel Support
– Mid-level Implementation Embedded Trace Macrocell
™
Bus Matrix
– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
– Boot Mode Select Option, Remap Command
Embedded Memories
– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed
– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
Dual External Bus Interface (EBI0 and EBI1)
– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
®
– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control
Twenty Peripheral DMA Controller Channels (PDC)
LCD Controller
– Supports Passive or Active Displays
– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers
Two D Graphics Accelerator
– Line Draw, Block Transfer, Clipping, Commands Queuing
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
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SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
•
– 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Two Real-time Timers (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE)
– 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
One Part 2.0A and Part 2.0B-compliant CAN Controller
– 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
Two Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard
™
Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
– Two SDCard Slots Support on eAch Controller
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA
®
Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
One Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel
®
EEPROMs Supported
IEEE
®
1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and VDDPLL
– 2.7V to 3.6V for VDDIOP0 (Peripheral I/Os)
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os)
Available in a 324-ball TFBGA Green Package
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
3
2.
SE
L
MASTER
N
T
TDRS
T
TDI
O
TM
TC S
SLA E
RT
JT C
AG
TC
TS L
TP NC
TPS0
-
0 TP
BM
-TP S2
S
15
L
C
LCDD
0
LCD S -LC
L D N D
C S C D
LCDD NC 23
O
LCDD TC
D EN
C
E
C
T
ET C -
E
EC EN R C
R -E
E S T -E
R -E E RE
ER ER CO R FC
- L
E 0 E
T -ER R D
EM 0-E 3
T
EMDC 3
EF DIO
10
0
D
P
D A
M
A
D
P
B
D
M
B
TST
Transc. Transc.
System
Controller
JTAG Boundary Scan
EBI0
EBI0
In-Circuit
Emulator
FI
IR 0-IR 1
AIC
ARM926EJ-S Processor
ETM
ICache
16 bytes
MMU
DCache
16 bytes
DBGU
TCM Interface
LCD
Controller
10/100 Ethernet
MAC
USB
O CI
FIFO
DMA
DMA
SDRAM
Controller
FIFO
LUT
FIFO
DMA
CompactFlash
NAND Flash
Figure 2-1. AT91SAM9263 Block Diagram
DR D
DT D
PC 0-PC 3
ITCM
DTCM
Bus Interface
PDC
PMC
I
D
PLLRCA
PLLA
PLLRCB
Fast SRAM
80 bytes
PLLB
IN
OUT
OSC
AT91SAM9263 Block Diagram
WDT
PIT
9-layer Bus Matrix
PIOA
PIOB
DMA
Peripheral
Bridge
PIOC
SRAM
16 bytes
DDCORE
Static
Memory
Controller
ECC
Controller
DDBU
20GPREG
RTT0
IN32
OUT32
OSC
RTT1
S DN
W UP
S DWC
2-channel
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDC , SDC E
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
A21/NANDALE
A22/NANDCLE
NWAIT
A23-A24
NCS4/CFCS0
NCS5/CFCS1
NCS3/NANDCS
A25/CFRNW
CFCE1-CFCE2
D16-D31
NCS2
POR
PIOE
ROM
128 bytes
APB
PIOD
RSTC
20-channel
Peripheral
DMA
DMA
EBI1
EBI1
NAND Flash
DDCORE
2D
Graphics
Controller
POR
NRST
SDRAM
Controller
PDC
SSC0
SSC1
USB
Device
Port
AC97C
DMA
PDC
PDC
CAN
SPI0
SPI1
PWMC
TC0
TC1
TC2
TWI
USART0
USART1
USART2
PDC
PDC
MCI0
MCI1
Image
Sensor
Interface
Static
Memory
Controller
ECC
Controller
Transc.
D0-D15
A0/NBS0
A1/NWR2
A2-A15/A18-A20
A16/BA0
A17/BA1
NCS0
NRD
NWR0/NWE
NWR1/NBS1
SDC
A21/NANDALE
A22/NANDCLE
NWAIT
NWR3/NBS3
NCS1/SDCS
NCS2/NANDCS
D16-D31
SDC E
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
SAM9263 [Summary]
SPI0 , SPI1
6249IS–ATARM–28-Jan-13
D
B
0-
D
B
D
A0 CD 3
-D B
A
C 3
DA
C
T
W
C TW
D
T
C
RS
T 0 -C
S C S 0- T S
R 2
R 0 T
D -S C S 2
T 0-R 2
D
0- D 2
T
D
2
CA
C
NT
AN
R
N
P
N CS
P 3
N C
P S2
N CS
PC 1
S S
PC 0
M
O
M
SI
PW
IS
O
M
0
-P
W
TC
M
L
3
T I 0 -T
O C
TI
A 0 L 2
O
-T
B 0
IO
-T
A 2
AC
IOB
2
A 9
C 7C
AC 97
F
AC97RS
9
T 7T
0
T F -T
TD 0-T1
R 0 -T F 1
D
D D
M
0 1
A
R
RF0-RD
0 R
-R 1
D 0-
F
M
ARR 1
1
3
I
SI I
D SI
0- P
IS IS C
I ID
IS S 11
I NC
S
IS NC
IM
C
MCI0 , MCI 1
D
D
D P
D
M
4
3.
Signal Description
Table 3-1
gives details on the signal name classified by peripheral.
Signal Description List
Function
Power Supplies
Type
Active
Level
Comments
Table 3-1.
Signal Name
VDDIOM0
VDDIOM1
VDDIOP0
VDDIOP1
VDDBU
VDDPLL
VDDOSC
VDDCORE
GND
GNDPLL
GNDBU
EBI0 I/O Lines Power Supply
EBI1 I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Backup I/O Lines Power Supply
PLL Power Supply
Oscillator Power Supply
Core Chip Power Supply
Ground
PLL Ground
Backup Ground
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
1.65V to 3.6V
1.65V to 3.6V
2.7V to 3.6V
1.65V to 3.6V
1.08V to 1.32V
3.0V to 3.6V
3.0V to 3.6V
1.08V to 1.32V
Clocks, Oscillators and PLLs
XIN
XOUT
XIN32
XOUT32
PLLRCA
PLLRCB
PCK0 - PCK3
Main Oscillator Input
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
PLL A Filter
PLL B Filter
Programmable Clock Output
Input
Output
Input
Output
Input
Input
Output
Shutdown, Wakeup Logic
SHDN
WKUP
Shutdown Control
Wake-up Input
ICE and JTAG
NTRST
TCK
TDI
TDO
TMS
JTAGSEL
RTCK
Test Reset Signal
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Return Test Clock
Input
Input
Input
Output
Input
Input
Output
No pull-up resistor
Pull-down resistor. Accepts
between 0V and VDDBU.
Low
Pull-up resistor
No pull-up resistor
No pull-up resistor
Output
Input
Driven at 0V only. Do not tie
over VDDBU.
Accepts between 0V and
VDDBU.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
5
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