5V9885TPFGI8 datasheet, PDF - EEWORLD Datasheet

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5V9885TPFGI8: DescriptionTQFP-32, Reel; CategoryMicrocontrollers and processors The clock generator; File Size716KB，40 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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TQFP-32, Reel

5V9885TPFGI8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LQFP, QFP32,.35SQ,32
Contacts	32
Manufacturer packaging code	PRG32
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Confidence	3
Samacsys Status	Released
Samacsys PartID	730036
Samacsys Pin Count	32
Samacsys Part Category	Integrated Circuit
Samacsys Package Category	Quad Flat Packages
Samacsys Footprint Name	PRG32-
Samacsys Released Date	2020-01-16 07:18:06
Is Samacsys	N
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	500 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Master clock/crystal nominal frequency	400 MHz
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	110 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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IDT5V9885T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

INDUSTRIAL TEMPERATURE RANGE

3.3V EEPROM

PROGRAMMABLE CLOCK

GENERATOR

FEATURES:

•

Three internal PLLs

Internal non-volatile EEPROM

JTAG and FAST mode I

C serial interfaces

Input Frequency Ranges: 1MHz to 400MHz

Output Frequency Ranges: 4.9kHz to 500MHz

Reference Crystal Input with programmable oscillator gain and

programmable linear load capacitance

−

Crystal Frequency Range: 8MHz to 50MHz

Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider

10-bit post-divider blocks

Fractional Dividers

Two of the PLLs support Spread Spectrum Generation

capability

I/O Standards:

−

Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS

−

Inputs - 3.3V LVTTL/ LVCMOS

Programmable Slew Rate Control

Programmable Loop Bandwidth Settings

Programmable output inversion to reduce bimodal jitter

Redundant clock inputs with glitchless auto and manual

switchover options

JTAG Boundary Scan

Individual output enable/disable

Power-down mode

3.3V V

Available in TQFP and VFQFPN packages

IDT5V9885T

DESCRIPTION:

The IDT5V9885T is a programmable clock generator intended for high

performance data-communications, telecommunications, consumer, and

networking applications. There are three internal PLLs, each individually

programmable, allowing for three unique non-integer-related frequencies.

The frequencies are generated from a single reference clock. The

reference clock can come from one of the two redundant clock inputs. A

glitchless automatic or manual switchover function allows any one of the

redundant clocks to be selected during normal operation.

The IDT5V9885T can be programmed through the use of the I

C or

JTAG interfaces. The programming interface enables the device to be

programmed when it is in normal operation or what is commonly known as

in-system programmable. An internal EEPROM allows the user to save

and restore the configuration of the device without having to reprogram it

on power-up. JTAG boundary scan is also implemented.

Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback

divider. This allows the user to generate three unique non-integer-related

frequencies. The PLL loop bandwidth is programmable to allow the user

to tailor the PLL response to the application. For instance, the user can tune

the PLL parameters to minimize jitter generation or to maximize jitter

attenuation. Spread spectrum generation and fractional divides are

allowed on two of the PLLs.

There are 10-bit post dividers on five of the six output banks. Two of the

six output banks are configurable to be LVTTL, LVPECL, or LVDS. The

other four output banks are LVTTL. The outputs are connected to the PLLs

via the switch matrix. The switch matrix allows the user to route the PLL

outputs to any output bank. This feature can be used to simplify and optimize

the board layout. In addition, each output's slew rate and enable/disable

function can be programmed.

•

INDUSTRIAL TEMPERATURE RANGE

2011

Integrated Device Technology, Inc.

SEPT. 2011

DSC 7117/4

5V9885TPFGI8 Related Products

	5V9885TPFGI8	5V9885TNLGI8	5V9885TPFGI
Description	TQFP-32, Reel	VFQFPN-28, Reel	TQFP-32, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Parts packaging code	TQFP	VFQFPN	TQFP
package instruction	LQFP, QFP32,.35SQ,32	QCCN, LCC28,.24SQ,25	LQFP, QFP32,.35SQ,32
Contacts	32	28	32
Manufacturer packaging code	PRG32	NLG28	PRG32
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	S-PQFP-G32	S-XQCC-N28	S-PQFP-G32
JESD-609 code	e3	e3	e3
length	7 mm	6.3 mm	7 mm
Humidity sensitivity level	3	1	3
Number of terminals	32	28	32
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Maximum output clock frequency	500 MHz	500 MHz	500 MHz
Package body material	PLASTIC/EPOXY	UNSPECIFIED	PLASTIC/EPOXY
encapsulated code	LQFP	QCCN	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32	LCC28,.24SQ,25	QFP32,.35SQ,32
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	CHIP CARRIER	FLATPACK
Peak Reflow Temperature (Celsius)	260	260	260
power supply	3.3 V	3.3 V	3.3 V
Master clock/crystal nominal frequency	400 MHz	400 MHz	400 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum slew rate	110 mA	110 mA	110 mA
Maximum supply voltage	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	NO LEAD	GULL WING
Terminal pitch	0.8 mm	0.65 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	NOT SPECIFIED	30
width	7 mm	6.3 mm	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)
Maximum seat height	1.6 mm	-	1.6 mm
Base Number Matches	1	1	-

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