HD74SSTV16857TEL datasheet, PDF

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HD74SSTV16857TEL: DescriptionD Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, TSSOP-48; Categorylogic; File Size70KB，15 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD74SSTV16857TEL Overview

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, TSSOP-48

HD74SSTV16857TEL Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP48,.3,20
Contacts	48
Reach Compliance Code	unknown
Is Samacsys	N
series	SSTV
JESD-30 code	R-PDSO-G48
length	12.5 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	14
Number of functions	1
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	2.5 V
propagation delay (tpd)	2.8 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	6.1 mm
minfmax	200 MHz
Base Number Matches	1

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HD74SSTV16857

1:1 14-bit SSTL_2 Registered Buffer

ADE-205-336E (Z)

6th. Edition

May 2000

Description

The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and

LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Data flow from D to Q is controlled by differential clock pins (CLK,

CLK)

and the

RESET.

Data is

triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to

maintain noise margins. When

RESET

is low, all registers are reset and all outputs are low.

To ensure defined outputs from the register before a stable clock has been supplied,

RESET

must be held in

the low state during power up.

Features

•

Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input

•

Differential SSTL_2 (Stub series terminated logic) CLK signal

•

Flow through architecture optimizes PCB layout

HD74SSTV16857TEL Related Products

	HD74SSTV16857TEL	HD74SSTV16857T
Description	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, TSSOP-48	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, TSSOP-48
Maker	Hitachi （Renesas ）	Hitachi （Renesas ）
Parts packaging code	TSSOP	TSSOP
package instruction	TSSOP, TSSOP48,.3,20	TSSOP, TSSOP48,.3,20
Contacts	48	48
Reach Compliance Code	unknown	unknown
Is Samacsys	N	N
series	SSTV	SSTV
JESD-30 code	R-PDSO-G48	R-PDSO-G48
length	12.5 mm	12.5 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Number of digits	14	14
Number of functions	1	1
Number of terminals	48	48
Maximum operating temperature	70 °C	70 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20	TSSOP48,.3,20
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	2.5 V	2.5 V
propagation delay (tpd)	2.8 ns	2.8 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	6.1 mm	6.1 mm
minfmax	200 MHz	200 MHz
Base Number Matches	1	1

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