Features
•
High Performance, Low Power Atmel
®
AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– 4 × 25 Segment LCD Driver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
– 54 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
Speed Grade:
– ATmega169PV: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 8 MHz @ 2.7V - 5.5V
– ATmega169P: 0 - 8 MHz @ 2.7V - 5.5V, 0 - 16 MHz @ 4.5V - 5.5V
Temperature range:
– -40°C to 85°C Industrial
Ultra-Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 330 µA
32 kHz, 1.8V: 10 µA (including Oscillator)
32 kHz, 1.8V: 25 µA (including Oscillator and LCD)
– Power-down Mode:
0.1 µA at 1.8V
– Power-save Mode:
0.6 µA at 1.8V (Including 32 kHz RTC)
•
•
•
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega169P
ATmega169PV
•
Preliminary
•
•
•
•
Rev. 8018P–AVR–08/10
ATmega169P
1. Pin Configurations
1.1
Pinout - TQFP/QFN/MLF
64A (TQFP) and 64M1 (QFN/MLF) Pinout ATmega169P
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF4 (ADC4/TCK)
PF7 (ADC7/TDI)
Figure 1-1.
PA0 (COM0)
PA1 (COM1)
50
61
60
59
58
57
56
55
54
53
52
51
64
63
62
49
48 PA3 (COM3)
47 PA4 (SEG0)
46 PA5 (SEG1)
45 PA6 (SEG2)
44 PA7 (SEG3)
43 PG2 (SEG4)
42 PC7 (SEG5)
41 PC6 (SEG6)
40 PC5 (SEG7)
39 PC4 (SEG8)
38 PC3 (SEG9)
37 PC2 (SEG10)
36 PC1 (SEG11)
35 PC0 (SEG12)
34 PG1 (SEG13)
33 PG0 (SEG14)
(SEG15) PD7 32
LCDCAP
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
INDEX CORNER
3
4
5
6
7
8
9
10
11
12
13
14
15
16
22
23
24
25
26
27
28
(OC2A/PCINT15) PB7 17
(T1/SEG24) PG3 18
(T0/SEG23) PG4 19
RESET/PG5 20
VCC 21
29
(SEG17) PD5 30
(SEG16) PD6 31
(ICP1/SEG22) PD0
(INT0/SEG21) PD1
(TOSC2) XTAL2
(TOSC1) XTAL1
GND
(SEG20) PD2
(SEG19) PD3
Note:
The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol-
dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen
from the board.
(SEG18) PD4
PA2 (COM2)
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
AVCC
AREF
GND
GND
VCC
2
8018P–AVR–08/10
ATmega169P
1.2
Pinout - DRQFN
64MC (DRQFN) Pinout ATmega169P
Figure 1-2.
Top view
A26
A34
B30
A33
B29
A32
B28
A31
B27
A30
B26
A29
B25
A28
B24
A27
B23
A26
Bottom view
B23
A27
B24
A28
B25
A29
B26
A30
B27
A31
B28
A32
B29
A33
B30
A34
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
B1
A1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A11
B10
A12
B11
A13
B12
A14
B13
A15
B14
A16
Table 1-1.
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
DRQFN-64 Pinout ATmega169P.
PE0
VLCDCAP
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PB0
PB1
PB2
PB3
PB5
PB4
A9
B8
A10
B9
A11
B10
A12
B11
A13
B12
A14
B13
A15
B14
A16
B15
A17
PB7
PB6
PG3
PG4
RESET
VCC
GND
XTAL2 (TOSC2)
XTAL1 (TOSC1)
PD0 (SEG22)
PD1 (SEG21)
PD2 (SEG20)
PD3 (SEG19)
PD4 (SEG18)
PD5 (SEG17)
PD7 (SEG15)
PD6 (SEG16)
A18
B16
A19
B17
A20
B18
A21
B19
A22
B20
A23
B21
A24
B22
A25
PG1 (SEG13)
PG0 (SEG14)
PC0 (SEG12)
PC1 (SEG11)
PC2 (SEG10)
PC3 (SEG9)
PC4 (SEG8)
PC5 (SEG7)
PC6 (SEG6)
PC7 (SEG5)
PG2 (SEG4)
PA7 (SEG3)
PA6 (SEG2)
PA4 (SEG0)
PA5 (SEG1)
A26
B23
A27
B24
A28
B25
A29
B26
A30
B27
A31
B28
A32
B29
A33
B30
A34
PA2 (COM2)
PA3 (COM3)
PA1 (COM1)
PA0 (COM0)
VCC
GND
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
AREF
AVCC
GND
B15
A17
B8
A10
B9
A9
A17
B15
A16
B14
A15
B13
A14
B12
A13
B11
A12
B10
A11
B9
A10
B8
A9
3
8018P–AVR–08/10
ATmega169P
2. Overview
The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut-
ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Block Diagram
Figure 2-1.
PF0 - PF7
PA0 - PA7
PC0 - PC7
VCC
GND
PORTF DRIVERS
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
ADC
AREF
INTERNAL
OSCILLATOR
CALIB. OSC
OSCILLATOR
JTAG TAP
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
LCD
CONTROLLER/
DRIVER
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
RESET
CONTROL
LINES
ALU
EEPROM
AVR CPU
STATUS
REGISTER
USART
UNIVERSAL
SERIAL INTERFACE
SPI
ANALOG
COMPARATOR
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG.
PORTG
XTAL1
XTAL2
DATA DIR.
REG. PORTG
+
-
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
4
8018P–AVR–08/10
ATmega169P
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega169P provides the following features: 16 Kbytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip
Debugging support and programming, a complete On-chip LCD controller with internal step-up
voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a
serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-
channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer and the LCD controller continues to run, allowing the user to maintain a timer base and
operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com-
bined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flex-
ible and cost effective solution to many embedded control applications.
The ATmega169P AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
5
8018P–AVR–08/10
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