W83977EF-PW datasheet, PDF - EEWORLD Datasheet

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W83977EF-PW: DescriptionWINBOND I/O; CategoryThe embedded processor and controller Microcontrollers and processors; File Size993KB，161 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W83977EF-PW Overview

WINBOND I/O

W83977EF-PW Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	QFP
package instruction	FQFP, QFP128,.67X.93,20
Contacts	128
Reach Compliance Code	unknow
Address bus width	16
boundary scan	NO
Bus compatibility	IBM XT; AT; ISA; PS/2
maximum clock frequency	48 MHz
External data bus width	8
JESD-30 code	R-PQFP-G128
length	20 mm
Number of I/O lines	22
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.32 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm

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W83977EF/CTF

WINBOND I/O

W83977EF/ CTF

PRELIMINARY

Table of Contents-

GENERAL DESCRIPTION..........................................................................................1

FEATURES .................................................................................................................2

PIN CONFIGURATION ...............................................................................................5

1.0 PIN DESCRIPTION..................................................................................................................... 6

1.1 HOST INTERFACE...................................................................................................................... 6

1.2 GENERAL PURPOSE I/O PORT ................................................................................................. 8

1.3 SERIAL PORT INTERFACE ........................................................................................................ 9

1.4 INFRARED INTERFACE............................................................................................................ 10

1.5 MULTI-MODE PARALLEL PORT............................................................................................... 11

1.6 FDC INTERFACE ...................................................................................................................... 16

1.7 KBC INTERFACE ...................................................................................................................... 18

1.8 POWER PINS............................................................................................................................ 18

1.9 ACPI INTERFACE ..................................................................................................................... 18

2.0 FDC FUNCTIONAL DESCRIPTION ...................................................................19

2.1 W83977EF/CTF FDC................................................................................................................. 19

2.1.1 AT interface ......................................................................................................................... 19

2.1.2 FIFO (Data) ......................................................................................................................... 19

2.1.3 Data Separator .................................................................................................................... 20

2.1.4 Write Precompensation........................................................................................................ 20

2.1.5 Perpendicular Recording Mode ............................................................................................ 21

2.1.6 FDC Core ............................................................................................................................ 21

2.1.7 FDC Commands .................................................................................................................. 21

2.2 REGISTER DESCRIPTIONS ..................................................................................................... 33

2.2.1 Status Register A (SA Register) (Read base address + 0) ................................................... 33

Publication Release Date: March 1999

Revision A1

-I -

W83977EF/ CTF

PRELIMINARY

2.2.2 Status Register B (SB Register) (Read base address + 1) ................................................... 35

2.2.3 Digital Output Register (DO Register) (Write base address + 2) ........................................... 37

2.2.4 Tape Drive Register (TD Register) (Read base address + 3)................................................ 37

2.2.5 Main Status Register (MS Register) (Read base address + 4).............................................. 38

2.2.6 Data Rate Register (DR Register) (Write base address + 4)................................................. 38

2.2.7 FIFO Register (R/W base address + 5) ................................................................................ 40

2.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................ 42

2.2.9 Configuration Control Register (CC Register) (Write base address + 7)................................ 43

3.0 UART PORT .......................................................................................................45

3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) .................... 45

3.2 REGISTER ADDRESS............................................................................................................... 45

3.2.1 UART Control Register (UCR) (Read/Write)......................................................................... 45

3.2.2 UART Status Register (USR) (Read/Write) .......................................................................... 47

3.2.3 Handshake Control Register (HCR) (Read/Write)................................................................. 48

3.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................. 49

3.2.5 UART FIFO Control Register (UFR) (Write only) .................................................................. 50

3.2.6 Interrupt Status Register (ISR) (Read only) .......................................................................... 51

3.2.7 Interrupt Control Register (ICR) (Read/Write) ....................................................................... 52

3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ..................................................... 52

3.2.9 User-defined Register (UDR) (Read/Write)........................................................................... 53

4.0 INFRARED (IR) PORTS......................................................................................54

4.1 IR PORT .................................................................................................................................... 54

4.2 CIR PORT(FOR W83977CTF ONLY) ........................................................................................ 54

4.2.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)........................................................ 54

4.2.2 Bank0.Reg1 - Interrupt Control Register (ICR) ..................................................................... 54

4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR)....................................................................... 55

4.2.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) ...... 56

4.2.5 Bank0.Reg4 - CIR Control Register (CTR) ........................................................................... 57

4.2.6 Bank0.Reg5 - UART Line Status Register (USR) ................................................................ 58

Publication Release Date: March 1999

Revision A1

-II -

W83977EF/ CTF

PRELIMINARY

4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ................................................. 58

4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR).............................................................. 59

4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ........................................................... 60

4.2.10 Bank1.Reg2 - Version ID Regiister I (VID) .......................................................................... 61

4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .... 61

4.2.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)................................................................. 61

4.2.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ............................................................... 61

4.3 DEMODULATION BLOCK DIAGRAM ........................................................................................ 62

5.0 PARALLEL PORT .............................................................................................63

5.1 PRINTER INTERFACE LOGIC .................................................................................................. 63

5.2 ENHANCED PARALLEL PORT (EPP) ....................................................................................... 64

5.2.1 Data Swapper..................................................................................................................... 65

5.2.2 Printer Status Buffer ............................................................................................................ 65

5.2.3 Printer Control Latch and Printer Control Swapper .............................................................. 66

5.2.4 EPP Address Port................................................................................................................ 66

5.2.5 EPP Data Port 0-3 ............................................................................................................... 67

5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................... 67

5.2.7 EPP Pin Descriptions.......................................................................................................... 68

5.2.8 EPP Operation..................................................................................................................... 68

5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .............................................................. 69

5.3.1 ECP Register and Mode Definitions ..................................................................................... 69

5.3.2 Data and ecpAFifo Port........................................................................................................ 70

5.3.3 Device Status Register (DSR)............................................................................................. 70

5.3.4 Device Control Register (DCR) ............................................................................................ 71

5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ....................................................................... 72

5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................... 72

5.3.7 tFifo (Test FIFO Mode) Mode = 110.................................................................................... 72

5.3.8 cnfgA (Configuration Register A) Mode = 111 ..................................................................... 72

5.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................... 72

5.3.10 ecr (Extended Control Register) Mode = all ....................................................................... 73

Publication Release Date: March 1999

Revision A1

-III -

W83977EF-PW Related Products

	W83977EF-PW	W83977CTF	W83977CTF-PW	W83977CTF-AW
Description	WINBOND I/O	WINBOND I/O	WINBOND I/O	WINBOND I/O
Maker	Winbond Electronics Corporation	-	Winbond Electronics Corporation	Winbond Electronics Corporation
Parts packaging code	QFP	-	QFP	QFP
package instruction	FQFP, QFP128,.67X.93,20	-	FQFP, QFP128,.67X.93,20	FQFP, QFP128,.67X.93,20
Contacts	128	-	128	128
Reach Compliance Code	unknow	-	unknow	unknow
Address bus width	16	-	16	16
boundary scan	NO	-	NO	NO
Bus compatibility	IBM XT; AT; ISA; PS/2	-	IBM XT; AT; ISA; PS/2	IBM XT; AT; ISA; PS/2
maximum clock frequency	48 MHz	-	48 MHz	48 MHz
External data bus width	8	-	8	8
JESD-30 code	R-PQFP-G128	-	R-PQFP-G128	R-PQFP-G128
length	20 mm	-	20 mm	20 mm
Number of I/O lines	22	-	22	22
Number of terminals	128	-	128	128
Maximum operating temperature	70 °C	-	70 °C	70 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	-	FQFP	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20	-	QFP128,.67X.93,20	QFP128,.67X.93,20
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, FINE PITCH	-	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
power supply	5 V	-	5 V	5 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	3.32 mm	-	3.32 mm	3.32 mm
Maximum supply voltage	5.5 V	-	5.5 V	5.5 V
Minimum supply voltage	4.5 V	-	4.5 V	4.5 V
Nominal supply voltage	5 V	-	5 V	5 V
surface mount	YES	-	YES	YES
technology	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	-	GULL WING	GULL WING
Terminal pitch	0.5 mm	-	0.5 mm	0.5 mm
Terminal location	QUAD	-	QUAD	QUAD
width	14 mm	-	14 mm	14 mm

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