Features/Benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
Extended Temperature Range for Very High Temperature up to 125°C
Very Low Power Consumption in Active, Power-down and Sleep Mode
2-Kbyte ROM, 256
´
4-bit RAM
12 Bi-directional I/Os
Up to 6 External/Internal Interrupt Sources
Multifunction Timer/Counter
Programmable System-clock with Prescaler and Five Different Clock Sources
Wide Supply-voltage Range (1.8 V to 6.5 V)
Very Low Sleep Current (< 1 µA)
Synchronous Serial Interface (2-wire, 3-wire)
Watchdog, POR and Brown-out Function
Voltage Monitoring Inclusive Lo_BAT Detect
Flash Controller ATAM893 Available (SSO20)
Description
The ATAR080-D is a member of Atmel’s family of 4-bit single-chip microcontrollers. It
contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter with modulator function, voltage supervisor, interval timer with watchdog
function and a sophisticated on-chip clock generation with external clock input, inte-
grated RC-, 32-kHz and 4-MHz crystal-oscillators.
Figure 1.
Block Diagram
V
SS
V
DD
NRST/
OSC1 OSC2
Low-current
Microcontroller
for Wireless
Communication
ATAR080-D
Brown-out protect
RESET
Voltage monitor
External input
VMI
External
RC
Crystal
oscillators oscillators clock input
Clock management
UTCM
Timer 1
interval- and
watchdog timer
ROM
2 K x 8 bit
RAM
256 x 4 bit
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Data direction
BP20/NTE
Port 2
BP21
BP22
BP23
MARC4
4-bit CPU core
I/O bus
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
BP40
BP42
T2O
INT3
SC
BP41
BP43
VMI
INT3
SD
T2I
BP50
INT6
BP52
INT1
BP53
INT1
BP51
INT6
Rev. 4676B–4BMCU–12/03
Pin Configuration
Figure 2.
Pinning SSO20
VDD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
NRST/OSC2
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
NC
NC
ATAR080-D
16
15
14
13
12
11
Pin Description
Pin
VDD
VSS
NC
NC
BP20
BP21
BP22
BP23
BP40
BP41
BP42
BP43
BP50
BP51
BP52
BP53
NC
NC
OSC1
NRST/
OSC2
Type
–
–
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
I
I/O
O
Function
Supply voltage
Circuit ground
Not connected
Not connected
Bi-directional I/O line of Port 2.0
Bi-directional I/O line of Port 2.1
Bi-directional I/O line of Port 2.2
Bi-directional I/O line of Port 2.3
Bi-directional I/O line of Port 4.0
Bi-directional I/O line of Port 4.1
Bi-directional I/O line of Port 4.2
Bi-directional I/O line of Port 4.3
Bi-directional I/O line of Port 5.0
Bi-directional I/O line of Port 5.1
Bi-directional I/O line of Port 5.2
Bi-directional I/O line of Port 5.3
Not connected
Not connected
Oscillator input
Reset input/output
Oscillator output
Alternate Funtion
–
–
–
–
NTE test mode enable, see also section “Master Reset”
–
–
–
SC serial clock or INT3 external interrupt input
VMI voltage monitor input or T2I external clock input
Timer 2
T2O Timer 2 output
SD serial data I/O or INT3-external interrupt input
INT6 external interrupt input
INT6 external interrupt input
INT1 external interrupt input
INT1 external interrupt input
–
–
4-MHz crystal input or 32-kHz crystal input or external
clock input or external trimming resistor input
4-MHz crystal output or 32-kHz crystal output or NRST
(mask option) or external clock input
Pin No.
SSO20
1
20
10
11
13
14
15
16
2
17
18
19
6
5
4
3
9
12
7
8
Reset
State
NA
NA
–
–
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
–
Input
NA
2
ATAR080-D
4676B–4BMCU–12/03
ATAR080-D
Introduction
The ATAR080-D is a member of Atmel's family of 4-bit single-chip microcontrollers.
They contain ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter, voltage supervisor, interval timer with watchdog function and a sophisti-
cated on-chip clock generation with integrated RC-, 32-kHz crystal- and 4-MHz crystal-
oscillators.
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and
on-chip peripherals. The CPU is based on the Harvard architecture with physically sep-
arated program memory (ROM) and data memory (RAM). Three independent buses,
the instruction bus, the memory bus and the I/O bus, are used for parallel communica-
tion between ROM, RAM and peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous communication to the on-chip
peripheral circuitry. The extremely powerful integrated interrupt controller with associ-
ated eight prioritized interrupt levels supports fast and efficient processing of hardware
events. The MARC4 is designed for the high-level programming language qFORTH.
The core includes both, an expression and a return stack. This architecture enables
high-level language programming without any loss of efficiency or code density.
Figure 3.
MARC4 Core
MARC4 CORE
Reset
Program
memory
PC
X
Y
SP
RP
RAM
256 x 4-bit
Reset
Clock
Instruction
bus
Memory bus
Instruction
decoder
TOS
CCR
Interrupt
controller
I/O bus
ALU
System
clock
Sleep
On-chip peripheral modules
3
4676B–4BMCU–12/03
Components of MARC4
Core
Figure 4.
ROM Map
7FFFh
1F8h
1F0h
1E8h
1E0h
1 E0h
1C0h
180h
I NT 7
I NT 6
I NT 5
I NT 4
I NT 3
I NT 2
I NT 1
I NT 0
SCALL addresses
ROM
(2 K x 8 bit)
Z er o
p age
140h
100h
0C0h
080h
040h
1FFh
Zero page
000h
020 h
018h
010h
008h
000 h
008h
000h
$R E SE T
$A U T O SL E E P
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruc-
tion decoder and interrupt controller. The following sections describe each functional
block in more detail:
ROM
The program memory (ROM) is mask programmed with the customer application pro-
gram during fabrication of the microcontroller. The ROM is addressed by a 12-bit wide
program counter, thus predefining a maximum program bank size of 2 Kbytes. An addi-
tional 1-Kbyte of ROM exists which is reserved for quality control self-test software The
lowest user ROM address segment is taken up by a 512-byte Zero page which contains
predefined start addresses for interrupt service routines and special subroutines acces-
sible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4. Look-up tables of constants can
also be held in ROM and are accessed via the MARC4's built-in table instruction.
RAM
The ATAR080-D contains 256 x 4-bit wide static random access memory (RAM) which
is used for the expression stack. The return stack and data memory are used for vari-
ables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address
registers SP, RP, X and Y.
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands from, and return
their results to the expression stack. The MARC4 performs the operations with the top
of stack items (TOS and TOS-1). The TOS register contains the top element of the
expression stack and works in the same way as an accumulator. This stack is also used
for passing parameters between subroutines and as a scratch pad area for temporary
storage of data.
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
Expression Stack
Return Stack
4
ATAR080-D
4676B–4BMCU–12/03
ATAR080-D
Figure 5.
RAM Map
(256 x 4-bit)
Autosleep
FCh
FFh
Global
variables
RAM
Expression stack
3
0
TOS
TOS-1
TOS-2
4-bit
Expression
stack
Return
stack
SP
RAM address register:
X
Y
SP
RP
04h
00h
07h
03h
TOS-1
Return stack
11
0
RP
Global
v
variables
12-bit
Registers
The microcontroller has seven programmable registers and one condition code register
(see Figure 6).
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches), the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the TABLE instruc-
tion to fetch 8-bit wide ROM constants.
Program Counter (PC)
Figure 6.
Programming Model
11
0
PC
7
0
Program counter
RP
7
0
0
0
Return stack pointer
SP
7
0
Expression stack pointer
X
7
0
RAM address register (X)
Y
3
0
RAM address register (Y)
TOS
3
0
Top of stack register
CCR
C
--
B
I
Condition code register
Interrupt enable
Branch
Reserved
Carry/borrow
5
4676B–4BMCU–12/03
京公网安备 11010802033920号
EEWORLD
