Features
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80C51 Compatible CPU Core High-speed Architecture
X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
16 MHz in Standard or X2 mode
256 Bytes RAM
256 Bytes XRAM
12K Bytes ROM/OTP Program Memory
Two 16-bit Timer/Counters T0, T1
5 Channels Programmable Counter Array with High-speed Output, Compare/Capture,
Pulse Width Modulation and Watchdog Timer Capabilities
SPI Interface (Master and Slave mode)
Interrupt Structure with:
– 6 Interrupt Sources
– 4 Interrupt Priority Levels
Power Supply: 3 - 5.5V
Temperature Range: Industrial (-40
o
C to 85
o
C), Automotive (-40
o
C to 125
o
C)
Package: SSOP16, SSOP24
Low-pin Count
8-bit
Microcontroller
AT87C5103
AT83C5103
Description
The AT8xC5103 is a high-performance ROM/OTP version of the 80C51 8-bit Micro-
controller in 16 and 24-pin packages.
The AT8xC5103 contains a standard C51 CPU core with 12 Kbytes ROM/OTP pro-
gram memory, 256 bytes of internal RAM, 256 bytes of extended internal RAM, a 5-
sources 4-level interrupt system, two timer/counters and a SPI serial bus controller.
The AT8xC5103 is also dedicated for analog interfacing applications. For this, it has a
five channels Programmable Counter Array.
In addition, the AT8xC5103 implements the X2 speed improvement mechanism. The
X2 feature allows to keep the same CPU power at a divided by two oscillator
frequency.
The fully static design of the AT8xC5103 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
Rev. 4134C–8051–09/04
1
Block Diagram
ECI
CEX0-4
(1) (1)
XTAL1
XTAL2
ROM
12 K *8
IB-bus
MISO
MOSI
SPSCK
SS
(1)(1)(3)(1)
SPI
P4
Vcc
Vss
Xtal
Osc
EXRAM
RAM
256x8
256x8
PCA
C51
CORE
CPU
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports
Port 1Port 3 Port 4
(3) (3)
(3) (3)
RST
INT0
INT1
T1
T0
Notes:
1. Alternate function of Port 1.
2. Alternate function of Port 3.
2
AT8xC5103
4134C–8051–09/04
P1
P3
AT8xC5103
Pin Configurations
P3.2/DIG0/INT0
P3.4/DIG1/T0
P3.6/SPICK
VSS
VCC
RST/VPP
XTAL2
XTAL1
1
2
3
4
5
6
7
8
16
15
14
SSOP16
13
12
11
10
9
P1.7/CEX4/SS
P1.6/CEX3
P1.5/CEX2
P1.4/CEX1
P1.3/CEX0
P1.2/ECI/DIG2
P1.1/MOSI
P1.0/MISO
P3.2/DIG0/INT0
P3.3/INT1
P3.4/DIG1/T0
P3.5/T1
P3.6/SPICK
VSS
VCC
RST/VPP
XTAL2
9
XTAL1
10
P4.0
11
P4.1
12
1
2
3
4
5
6
7
8
SSOP24
24
23
22
21
20
19
18
17
16
15
14
13
P3.1
P3.0
P1.7/CEX4/SS
P1.6/CEX3
P1.5/CEX2
P1.4/CEX1
P3.7
P1.3/CEX0
P1.2/ECI/DIG2
P4.2
P1.1/MOSI
P1.0/MISO
3
4134C–8051–09/04
Pin Description
Mnemonic
V
SS
V
CC
P1.0 - P1.7
Type
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XTAL1
XTAL2
RST/VPP
I
I
O
Name and Function
Ground:
0V reference
Power Supply:
3.0V or 5.5V
Port 1:
Port 1 is an 8-bit programmable I/O port with internal pull-up
Alternate functions for Port 1 include:
MISO (P1.0):
Master IN, Slave OUT of the SPI controller
MOSI (P1.1):
Master OUT, Slave IN of the SPI controller
DIG2 (P1.2):
Programmable as Output with Push-pull
ECI:
External Clock for PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
SS (P1.7):
Slave select input of the SPI controller
CEX4:
Capture/Compare External I/O for PCA module 3
Input to the inverting oscillator amplifier
Output from the inverting oscillator amplifier
RST:
Negative Reset input
A low on this pin for two machine cycles while the oscillator is running,
resets the device.
This pin will include a pull-down to reset the circuit if no external reset
level is applied.
VPP:
High voltage input for OTP programming
Port 3:
Port 3 is a 8-bit programmable I/O port with internal pull-up.
P3.0:
Programmable as Output with Push-pull.
P3.1:
Programmable as Output with Push-pull.
DIG0 (P3.2):
Programmable as Output with Push-pull.
INT0:
External Interrupt 0
P3.3:
Programmable as Output with Push-pull.
INT1:
External Interrupt 1
DIG1 (P3.4):
Programmable as Output with Push-pull.
T0:
Timer 0 external Input
P3.5:
Programmable as Output with Push-pull.
T1:
Timer 1 external Input
SPICK (P3.6):
Clock I/O of the SPI controller
P3.7:
Programmable as Output with Push-pull.
Port 4:
Port 4 is an 3-bit I/O port with internal pull-up
P3.0 - P3.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P4.0-P4.2
I/O
4
AT8xC5103
4134C–8051–09/04
AT8xC5103
Clock
The Errata Sheet core needs only 6 clock periods per machine cycle. This feature,
called ”X2”, provides the following advantages:
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Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU
power.
Saves power consumption while keeping the same CPU power (oscillator power
saving).
Saves power consumption by dividing dynamic operating frequency by 2 in
operating and idle modes.
Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by the software.
Description
The clock for the whole circuit and peripheral is first divided by 2 before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. The X2
bit is validated on the XTAL1
÷
2 rising edge to avoid glitches when switching from the
X2 to the STD mode. Figure 2 shows the mode switching waveforms.
5
4134C–8051–09/04
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