Features
•
Compatible with MCS
®
-51 Products
•
20K Bytes of Reprogrammable Flash Memory
•
•
•
•
•
•
•
•
– Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 12 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Low-power Idle and Power-down Modes
2.7V to 6.0V Operating Range
1. Description
The AT89LV55 is a low-voltage, low-power CMOS 8-bit microcontroller with 20K bytes
of Flash programmable and erasable read-only memory. The device is manufactured
using Atmel’s high-density nonvolatile memory technology and is compatible with the
industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the pro-
gram memory to be reprogrammed. By combining a versatile 8-bit CPU with Flash on
a monolithic chip, the Atmel AT89LV55 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89LV55 provides the following standard features: 20K bytes of Flash,
256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level
interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT89LV55 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power-down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next hardware reset.
The low-voltage option saves power and operates with a 2.7-volt power supply.
8-bit
Microcontroller
with 20K Bytes
Flash
AT89LV55
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2. Pin Configurations
2.1
44A – 44-lead TQFP
2.2
40P6 – 40-lead PDIP
2.3
44J – 44-lead PLCC
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AT89LV55
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AT89LV55
3. Block Diagram
P0.0 - P0.7
P2.0 - P2.7
V
CC
PORT 0 DRIVERS
GND
PORT 2 DRIVERS
RAM ADDR.
REGISTER
RAM
PORT 0
LATCH
PORT 2
LATCH
FLASH
B
REGISTER
ACC
STACK
POINTER
PROGRAM
ADDRESS
REGISTER
BUFFER
TMP2
TMP1
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PC
INCREMENTER
PSW
PROGRAM
COUNTER
PSEN
ALE/PROG
EA / V
PP
RST
PORT 1
LATCH
PORT 3
LATCH
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
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4. Pin Description
4.1
V
CC
Supply voltage.
4.2
GND
Ground.
4.3
Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pullups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification.
External pullups are required during program verification.
4.4
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-
nal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (I
IL
) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-
ing table.
Port Pin
P1.0
P1.1
Alternate Functions
T2 (external count input to Timer/Counter 2), clock-out
T2EX (Timer/Counter 2 capture/reload trigger and direction control)
Port 1 also receives the low-order address bytes during Flash programming and verification.
4.5
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-
nal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low
will source current (I
IL
) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external program memory and dur-
ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash program-
ming and verification.
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AT89LV55
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AT89LV55
4.6
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-
nal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (I
IL
) because of the pullups.
Port 3 also serves the functions of various special features of the AT89LV55, as shown in the
following table.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Port 3 also receives the highest-order address bit and some control signals for Flash program-
ming and verification.
4.7
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device.
4.8
ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
4.9
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT89LV55 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to exter-
nal data memory.
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