KM68B261A
32K x 8 Bit High-Speed BiCMOS Static RAM
FEATURES
• Fast Access Time 6,7,8ns(Max.)
• Low Power Dissipation
Standby (TTL) : 110 mA(Max.)
(CMOS) : 20 mA(Max.)
Operating Current : 170 mA(f=100MHz)
• Single 5V ± 5% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68B261AJ : 32-SOJ-300
BiCMOS SRAM
GENERAL DESCRIPTION
The KM68B261A is a 262,144-bit high-speed Static
Random Access Memory organized as 32,768 words by
8 bits. The KM68B261A uses eight common input and
output lines and has an output enable pin which
operates faster than address access time at read cycle.
The device is fabricated using Samsung`s advanced
BiCMOS process and designed for high-speed system
applications. It is particularly well suited for use in high-
density high-speed system applications. The
KM68B261A is packaged in a 300 mil 32-pin plastic
SOJ.
FUNCTIONAL BLOCK DIAGRAM
Pre-Charge Circuit
PIN CONFIGURATION
(TOP VIEW)
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
N.C
A14
A13
A12
/OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A11
A10
A9
A8
N.C
A0
A1
A2
A3
A4
A5
A6
Row Select
MEMORY ARRAY
128 Rows
256x8 Columns
A3
/CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
/WE
A4
Data
Cont.
I/O Circuit
Column Select
A5
A6
A7
SOJ
25
24
23
22
21
20
19
18
17
I/O1-I/O8
A7 A8 A9 A10 A11 A12 A13 A14
PIN DESCRIPTION
Pin Name
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power (5V)
Ground
No Connection
A0-A14
/WE
/CS
/OE
I/O1-I/O8
Vcc
Vss
N.C
/CS
/WE
/OE
1
Rev 2.0
October-1994
KM68B261A
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
VIN,OUT
Vcc
PD
Tstg
TA
BiCMOS SRAM
Rating
- 0.5 to 7.0
- 0.5 to 7.0
1.0
- 65 to 150
0 to 70
Unit
V
V
W
°C
°C
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA= 0 to 70 °C )
Parameter
Supply Voltage
Ground
Input Low Voltage
Input High Voltage
Symbol
Vcc
Vss
VIH
VIL
Min
4.75
0
2.2
-0.5*
Typ.
5.0
0
-
-
Max
5.25
0
Vcc+0.5**
0.8
Unit
V
V
V
V
* V
IL
(Min) = -2.0 (Pulse Width
≤3ns)
for I
≤
20mA
** V
IH
(Max) = Vcc+2.0V(Pulse width
≤
8ns)for I
≤
20mA
(TA= 0 to 70°C, Vcc=5 V
±
5%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Symbol
ILI
ILO
ICC
ISB
ISB1
Output Low Voltage
Output High Voltage
VOL
VOH
Test Conditions
VIN=Vss to Vcc
/CS=VIH or /OE=VIH or /WE=VIL
V
OUT
=V
SS
to Vcc
f=100MHz, 100% Duty, /CS=VIL,
VIN=VIH or VIL, IOUT=0mA
Min. Cycle, /CS=VIH
f=0MHz, /CS
≥
Vcc-0.2V,
VIN
≥
Vcc -0.2V or VIN
≤
0.2V
IOL=8mA
IOH = - 4mA
-
2.4
0.4
-
V
V
-
-
110
20
mA
mA
-
170
mA
Min
-10
-10
Max
10
10
Unit
µA
µA
DC AND OPERATING CHARACTERISTICS
2
Rev 2.0
October-1994
KM68B261A
CAPACITANCE*
(f=1MHz, TA =25 °C)
Item
Input Capacitance
Input/Output Capacitance
Symbol
CIN
CI/O
Test Condition
VIN=0V
VI/O=0V
BiCMOS SRAM
Min.
-
-
Max.
7
7
Unit
pF
pF
* Note: Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS
TEST CONDITIONS ON DATA RAM
(TA= 0 to 70°C, Vcc=5V
±
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5%, unless otherwise specified.)
Value
0 to 3 V
3ns
1.5V
See below
Output Load (A)
Output Load (B)
for tHZ, tLZ, tWHZ, tOW, tOLZ, & tOHZ
DOUT
Z
O
=50
Ω
DOUT
R
L
=50
Ω
255
Ω
V
L
=1.5V
+5V
480
Ω
5pF*
* Including Scope and Jig Capacitance
3
Rev 2.0
October-1994
KM68B261A
READ CYCLE
KM68B261A-6
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Symbol
Min
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
6
-
-
-
3
1
0
0
3
Max
-
6
6
4
-
-
3
3
-
Min
7
-
-
-
3
1
0
0
3
BiCMOS SRAM
KM68B261A -7
Max
-
7
7
4
-
-
3.5
3.5
-
KM68B261A -8
Unit
Min
8
-
-
-
3
1
0
0
3
Max
-
8
8
4
-
-
4
4
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
KM68B261A -6
Parameter
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width(/OE High)
Write Pulse Width(/OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
Min
tWC
tCW
tAS
tAW
tWP
tWP
tWR
tWHZ
tDW
tDH
tOW
6
6
0
3.5
3.5
6
1
0
3
0
3
Max
-
-
-
-
-
-
-
3
-
-
-
Min
7
7
0
4
4
7
1
0
3.5
0
3
Max
-
-
-
-
-
-
-
3.5
-
-
-
Min
8
8
0
4.5
4.5
8
1
0
4
0
3
Max
-
-
-
-
-
-
-
4
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
KM68B261A -7
KM68B261A -8
Unit
4
Rev 2.0
October-1994
KM68B261A
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE
Address
tAA
tCO
/CS
(/WE=VIH)
tRC
BiCMOS SRAM
t HZ(3,4,5)
tOHZ
tOE
/OE
tOLZ
t LZ (4,5)
Data Valid
tOH
Data Out
NOTES (READ CYCLE)
High-Z
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referenced to VOH or VOL levels.
4. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and
from device to device.
5. Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not
100% tested.
6. Device is continuously selected with /CS=VIL
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read
and write cycle.
TIMING WAVE FORM OF WRITE CYCLE(1)
Address
(/OE=Clock)
tRC
tAW
/OE
tCW(3)
/CS
tAS(4)
/WE
tDW
High-Z
Data In
tOHZ(6)
High-Z(8)
Data Out
5
Data Valid
tOW
t WP(2)
t WR(5)
tDH
Rev 2.0
October-1994
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