MAY 1996
ADVANCE INFORMATION
DS4054-2.2
WL100
WLAN INTERFACE CIRCUIT
The WL100, together with the DE6003 frequency hopping
radio transceiver, implements a wide variety of WLAN
applications where NRZ encoding is used.
B_DATA0
B_DATA1
B_DATA2
B_DATA3
B_DATA4
B_DATA5
B_DATA6
V
SS
V
DD
B_DATA7
B_ADDR0
B_ADDR1
B_ADDR2
B_ADDR3
B_ADDR4
CS
FEATURES
I
Low Power CMOS Technology
I
Flexible Data Transceiver
I
Clock Recovery with Continuous Calibration for
Flexible Packet Length
I
Flexible Preamble Format
I
Selectable Data Rates: 156·25kb/s, 250kb/s,
312·5kb/s, 500kb/s, 625kb/s and 1Mb/s
I
CRC-32 Generator/Checker
I
Fast Antenna Diversity with Manual Override
I
Battery Level Monitoring
I
8-Bit Parallel Controller Interface
RELATED DOCUMENTS
DE6003 data sheet, DS3506
GPS application notes AN142,143,144,145, 154 and 203
for further design information.
PIN 1
PIN 64
NC
NC
IRQ
V
SS
V
BAT
SHCAP
RSSI
NC
NC
V
REF
STDBY
V
DD
ANTSEL
V
SS
NC
NC
RD
WR
RESET
CKSEL1
CKSEL0
E_CLK
V
DD
V
SS
B_CLK
C_CLK
TEST
ATSTIN
ATSTOUT
XCKT
RXD
SYNLOK
PIN 1 IDENT
WL100
PAOFF
PWRLO
RX/TX
TXD
LOADB
SD6
SD5
V
DD
V
SS
CLK
NC
SD4
SD3
SD2
SD1
SD0
ORDERING INFORMATION
WL100/CG/FP1R
- Commercial, Quad Plastic Flatpack
Prior to completion of full device characterisation, pre-
production parts will be designated
WL100/PR/FP1R.
FP64
Fig. 1 Pin connections (top view). See Table 8 for pin
descriptions.
DE6003
FREQUENCY
HOPPING
TRANSCEIVER
WL100
WLAN INTERFACE CIRCUIT
WLAN
MAC
CONTROLLER
HOST
MICRO-
PROCESSOR
Fig. 2 WLAN system block diagram
WL100
GENERAL FUNCTIONALITY
Fig. 4 shows the WL100 Block Diagram and its interaction
with the DE6003 and a generic WLAN Media Access Controller
(MAC) layer Controller, referred to in the following text as the
Controller. The format of a generic data burst/packet that the
WL100 receives on the RXD line is shown in Fig. 3. On the
radio side, the WL100 conforms to the DE6003 specifications.
On the Controller side the WL100 conforms to the general 8-bit
Controller external bus specifications. All WL100 registers are
accessed by the Controller through the 8-bit B_DATA bus. A
typical Controller I/O read/write timing is shown in Fig. 15.
There are five types of registers internal to the WL100 which the
Controller can access via the B_DATA bus: Control Registers (write
only), Status Registers (read only), Configuration registers (write
only), FIFO (read/write) and Data Length Registers (write only).
The Controller uses the control registers to initiate a particular
WL100 function. The bit definitions for the WL100 control
registers are shown in Fig. 5.
SYNC
WORD
SYNC
WORD
SYNC
WORD
The status registers are used to inform the Controller about
the WL100 and DE6003 status. Fig. 6 shows the bit definitions
for the WL100 status registers. The Controller makes the decision
about a channel status according to the table in Fig. 6.
Fig. 7 shows the 1638 receive/transmit FIFO and the data
length register. The FIFO buffers the data going to/coming from
the Controller and provides an uninterrupted data flow between
the WL100 and DE6003 at different data rates and system clock
speeds. The data length register is used for the CRC calculations
during data receive.
The configuration registers are shown in Figs. 8 and 9.
They give flexibility to the WL100 so that it can be used in a
number of different system applications. Configuration
registers can be written to only when the Commence Diversity
(CD), Commence Transmission (CT), Commence Reception
(CR) and Commence Hopping (CH) bits in a WL100 control
register are inactive (high).
10
100
CRC - 32
SYNCHRONISATION SEQUENCE
FRAME DELIMITER
HEADER
PREAMBLE
USER DATA
FCS
Fig 3 Generic data burst/packet format
Start address
00
03
04
08
0C
0D
10
1B
1C
1E
End address
02
-
07
0B
-
0F
1A
-
1D
1F
Description
Control registers
Unused
Status registers
Unused
FIFO
Unused
Configuration registers
Unused
Data length registers
Unused
stuffed bits, generates the CRC, converts the serial data into 8-
bit words and sends it to the Controller. Once all data have been
received, the WL100 checks CRC and writes four CRC bytes
into the FIFO in case the Controller needs to read them.
If the WL100 cannot recover the synchronisation sequence
within a predefined time, it returns a channel status to
the Controller.
BLOCK DIAGRAM DESCRIPTION
Receive/Transmit State Machine
The Receive/Transmit state machine controls the WL100-
to-DE6003 interface and is responsible for the receive/transmit
control timing, transmit power amplifier control timing, transmitter
power level control and channel load pulse timing.
To hop to a new frequency, the CH bit (Fig. 5, ADDR 01, bit 7)
has to be set to 0. As a result, a negative LOADB pulse is gen-
erated and will load the frequency data SD (0:6) (Fig. 5, ADDR
01, bits 0 to 6) into the DE6003. The Controller does not need to
reset the CH bit as the WL100 carries this out as part of the
channel select sequence.
To start data transfer, the Controller must set the CT bit to 0
(Fig.5, ADDR 00, bit 4). When all transmit data has been read
by the WL100, the CT bit must be reset to 1.
Table 1
Table 1 shows how the WL100 registers are mapped into its
address space.
The Controller activates the WL100 each time it wants to
scan the channel, receive data from the channel or transmit
data over it. Prior to the start of a transmit or a receive function,
the WL100 will drive the control signals to put the radio in a
required mode of operation, according to the DE6003
specification.
The Controller is responsible for updating the frequency
control register (Fig.5, ADDR 01), maintaining minimum time
between consecutive transmissions, maximum continuous
transmit time, radio standby to transmit time, frequency hopping
time for transmit and for receive and timely loading of the data
length register (Fig. 7, ADDR 1C and1D) for the CRC function.
In the transmit direction, the WL100 receives the user data
in 8-bit words from the Controller bus and converts it into a
serial data stream. After a preamble sequence has been
transmitted, the WL100 calculates CRC, does bit stuffing and
transmits a data stream to the radio, appending the CRC at the
end. Both transmit and receive data is buffered by the FIFO.
In the receive direction, the WL100 receives a serial NRZ
data stream from the radio, strips the preamble, removes the
Preamble Generator
A preamble is generated for every transmit data burst sent to
the DE6003 on TXD. The preamble is fully programmable ( see
Fig. 8, ADDR 12 and ADDR 13, bits 0:2 for a sync word bit
pattern, ADDR18 for the number of transmitted sync words, and
ADDR 13, bits 3:7 and ADDR 14 to 17 for the frame delimiter bit
pattern).
Bit Stuffing
The Bit Stuffing logic examines the data stream to the radio
and inserts an altered polarity bit relative to the last bit in a se-
lected bit group. A number of bits in a group can be programmed
(see Fig. 9, ADDR 19, bits 6 and 7). The DE6003 requires at
least one transition after every 16 bit times at 625kb/s data rate
to assure adequate bit error rate performance. Thus, to break
long sequences of ones or zeros at 312kb/s, bit stuffing after
2
ANT 1
XCKT
ANT 2
C_CLK
RXD
CLOCK RECOVERY
AND CCA
BIT
DESTUFFING
8
8
ADDR 07 (2:0)
MUX
ADDR 06 (7:6)
SERIAL/PARALLEL
CONVERTER
8
DATA
RECOVERY
B_DATA (7:0)
CONFIGURATION
REGISTERS
ADDR 12-17
ADDR 07(6:3)
PREAMBLE
GENERATOR
FIFO
CONTROL AND
FLAG LOGIC
(15)
FIFO
1638
(0)
MUX
8
8
MUX
TXD
ADDR 19 (7:6)
ADDR 06 (5.4)
M
U
X
BIT
STUFFING
M
U
X
CRC
GEN/CHK
M
U
X
STATUS
ADDR
04-07
PARALLEL/SERIAL
CONVERTER
C10MHz
B_CLK
CK800N, CK400N
ADDR 00 (2:0)
2
DIVERSITY
CONTROLLER
5
5
ADDR 00 (6)
ADDR 00 (7)
ADDR 04 (7, 6, 4:0)
ADDR 05 (6, 4:0)
2
BATTERY
MONITOR
CS
RD
WR
B_ADDR (4:0)
5
SUCCESSIVE
APPROXIMATION
REGISTER
CLOCK
SELECTOR/
GENERATOR
DE6003
CLK
CLK RCV
E_CLK
2
ADDR 01 (6:0)
ADDR 06 (0)
ADDR 06 (1)
ADDR 07 (7)
ADC CONTROL
Fig. 4 WL100 chip block diagram
RECEIVE /
TRANSMIT
STATE
MACHINE
ADC
V
BAT
V
REF
SHCAP
TEST
WLAN
MEDIA
ACCESS
CON-
TROLLER
(MAC)
CKSEL
ANTSEL
STDBY
PWRLO
LOADB
SD (6:0)
PAOFF
RX / TX
SYNLOK
7
RD/WR
CONTROL
AND
REGISTER
SELECT
INTERRUPT
LOGIC
IRQ
RESET
WL100
ATSTIN ATSTOUT
WL100
RSSI
3
WL100
8 bits will be required and for 156kb/s, bit stuffing after 4 bits will
be needed. The WL100 performs bit stuffing for user data only.
Preamble fields must be selected by a user in a way that a
maximum number of consecutive ones or zeros is not violated.
Bit stuffing also helps to distinguish between long strings of ones
or zeros in a valid data stream and a clear channel (no data and
no noise) by the Clear Channel Assessment (CCA) logic.
Full and Empty flags are also provided (Fig. 6, ADDR 06,
bits 2 and 3). All bits are set on the negative edge of the C_CLK
clock.
Parallel-to-Serial Converter
The Parallel-to-Serial Converter transforms parallel byte-wide
data from the FIFO or from the Preamble Generator to a serial
bit stream. The data from the FIFO is sent to the CRC Generator
and Bit Stuffing logic. The preamble is sent directly to the TXD
output of the chip.
Bit Destuffing
The Bit Destuffing logic monitors a data sequence from the
Data Recovery logic and strips the bits inserted by the bit stuff-
ing logic of the transmitter.
CRC Generator/Checker
The WL100 performs this optional function if instructed to do
so by the Controller (see Fig. 5, ADDR 02, bit 1). CRC is gener-
ated according to IEEE-802 standard 32-bit AUTODIN-II poly-
nomial.
During transmit the WL100 does not need to know the user
data byte count and will automatically append CRC when the
CT bit (Fig. 5, ADDR 00, bit 4) is high and the FIFO becomes
empty.
During receive the Controller has to provide the WL100 with
the data length information (Fig. 7, ADDR 1C and ADDR 1D)
some time before the end of a frame to let the WL100 know
when to check CRC.
Serial-to-Parallel Converter
This transforms a serial data stream from the bit destuffing
logic into parallel byte-wide format and sends it to the FIFO.
FIFO
The FIFO a 1638, fall-through type. During receive operation
it buffers the data coming from the Serial-to-Parallel Converter
and makes it available for the Controller to read over the B_DATA
bus. During transmit operation it buffers the data coming from
the B_DATA bus and makes it available to the Parallel-to-Serial
Converter.
FIFO Control and Flag Logic
The FIFO Control and Flag logic controls data flow through
the FIFO. Almost Full (AF) and Almost Empty (AE) flags (Fig. 6,
ADDR 07, bits 3 and 4) are programmable by FL 0 and FL1(Fig.
9, ADDR 1A, bits 5 and 6) and can be monitored by the Controller
as well as Read and Write error indication bits (Fig. 6, ADDR
07, bits 5 and 6). A Read error is caused by attempting to read
from the FIFO when it is empty; a Write error is caused by
attempting to write to the FIFO when it is full.
ADDR 01
7
CH
6
SD6
5
SD5
4
SD4
3
SD3
2
SD2
1
SD1
0
7
6
Clock Recovery and Clear Channel Assessment
(CCA)
The Clock Recovery and CCA logic recovers the data clock XCKT
from the RXD data stream, provides recovered clock to the Data
Recovery logic, and determines if the channel is busy or free to
transmit. The WL100 starts recovering clock each time the CR bit
(Fig. 5, ADDR 00, bit 3) is set low by the Controller. It must stay low
for the whole time of CCA or data receive function.
ADDR 00
5
4
CT
3
CR
2
1
0
CD
(d) = default state
0 = Commence Hopping
1 = Inactive (d)
Channel Select
(d = 0000000)
0 = Commence Auto Diversity
1 = Auto Diversity Inactive (d)
0 = Low power level (d)
1 = High power level
0 = Manual Diversity
1 = Auto Diversity (d)
(See Table 6)
0 = Reset All Registers
(Except CNTRL and CONFIG)
1 = Inactive (d)
0 = Manual ANT 1 (d)
1 = Manual ANT 2
(See Table 6)
0 = Sleep Mode (d)
1 = Operational Mode
0 = Commence Transmission (at least 1µs long)
1 = Stop Transmission (d)
0 = Commence Receive Function
1 = Stop Receive Function (d)
7
MSK7
6
5
0 = SYNLOK Enabled
1 = SYNLOK Disabled (d)
SD0 PWRL STDB RST
ANT2 MAN
ADDR 02
0 = Normal Operation Mode (d)
1 = Device Tests (Digital) Mode
4
3
2
1
0
DGT ECRC DBG
0 = CRC Disabled (TX) / DL Not Valid (RX)
1 = CRC Enabled (TX) / DL Is Valid (RX) (d)
0 = Normal Mode (d) XCKT when in Sync
1 = Debug Mode XCKT at all times
Fig. 5 Control registers (write only)
4
WL100
After the time limit for the synchronisation has expired, the
syncdone (SYDN) bit is set (Fig. 6, ADDR 07, bit 2) and interrupt
to the controller is generated. At this time the Controller can
make a decision about the channel status by examining noise
(NS) and long sequence (LONG) bits (Fig. 6, ADDR 07, bits 1
and 0).
Clock Recovery and CCA logic requires 16:1 ratio for an
oversampling clock C_CLK. Table 7 shows the oversampling
clock rate required for particular selected data transfer rates.
Read/Write Control and Register Select
The Read/Write Control and Register Select logic controls
the bidirectional B_DATA bus and selects the WL100 registers
during the Controller-initiated read and write operations.
Interrupt Logic
Interrupt logic generates interrupt requests to the Controller
when a certain WL100 status has to be reported. At that time,
IRQ becomes low and stays low until reset. Table 2 lists all
cases when the WL100 generates interrupts together with cor-
responding interrupt reset conditions.
Radio Synthesiser Unlocked interrupt can be disabled by
setting the MSK7 bit high (Fig. 5, ADDR 02, bit 7).
Data Recovery Logic
The Data Recovery logic detects the sequence of sync words
and the frame delimiter in the data stream supplied by the Clock
Recovery logic according to the Sync Word and Frame Word
configuration (see Fig. 8, ADDR 12 and ADDR 14 -17) and
separates it from the User Data. If NS or LONG bits (ADDR 07,
bits 1 and 0) have been set, the WL100 stops searching for
sync sequence. The Controller might choose to poll these bits
to get early indication of a free channel prior to expiration of
Syncdone Timer.
Once the sync sequence has been detected, the SYNC bit
(see Fig. 6, ADDR 06, bit 6) goes high and remains high until
the end of the data reception. The FRM bit (see Fig. 6, ADDR
06, bit 7) goes high when a frame delimiter has been detected
and stays on until the end of data reception.
Diversity Controller
The Diversity Controller automatically selects the optimum an-
tenna during receive operations. To start auto diversity, the Control-
ler has to set the auto diversity bit (Fig. 5, ADDR 00, bit 0) low, which
has to stay low for at least 1µs, when it can be switched back to high
at any time before another diversity function is to be initiated. The
circuit performs diversity by comparing the Receive Signal Strength
Indication (RSSI) energy levels from both antennas and selecting
the one which yields the higher level.
The Diversity Switch can also be controlled manually (Fig. 5,
ADDR 00, bits 1 and 2). The RSSI level can be checked at any
time by auto operation of the diversity (see Fig. 6, ADDR 04).
ADDR 05
7
6
BVAL
5
4
BT4
3
BT3
2
BT2
1
BT1
0
7
6
5
ADDR 04
4
DV4
3
DV3
2
DV2
1
DV1
0
DV0
(d) = default state
0 = DV Not Valid (d)
1 = DV Valid
0 = BT Not Valid (d)
1 = BT Valid
Battery Level
(See Table 10)
0 = Auto ANT 1 (d)
1 = Auto ANT 2
ADDR 07
7
6
5
4
AE
3
2
1
NS
0
7
6
5
ADDR 06
4
3
2
1
0
LCK WERR RERR
0 = Radio PLLs Locked
1 = Radio PLLs Unlocked
FIFO Write Error
FIFO Read Error
AF SYDN
LONG FRM SYNC
CRC
CRCE EMP FULL RXTX PAOF
RDY
0 = Power Amp. Off
1 = Power Amp. On
0 = Transmit in Progress
1 = No Transmit
0 = Buffer Not Full
1 = Buffer Full
0 = Buffer Not Empty
1 = Buffer Empty
0 = No CRC Error
1 = CRC Error
0 = CRC Not Ready
1 = CRC Checked
0 = No Synchronisation
1 = SYNC Achieved
0 = No Frame
1 = Frame Recognised
0 = No Long Sequence
1 = Long Sequence of ‘1’s or ‘0’s
0 = No Noise
1 = Noise
0 = Syncdone Timer Not Expired
1 = Syncdone Timer Expired
0 = Buffer Not Almost Full
1 = Buffer Almost Full
0 = Buffer Not Almost Empty
1 = Buffer Almost Empty
Channel status (ADDR 07, bits 2:0)
SYDN
1
1
1
NS
0
1
X
LONG
0
X
1
Status
Channel is busy
Channel is clear
to transmit
Fig. 6 Status registers (read only)
RSSI Level
(See Table 9)
BT0 AUT2 DVAL
5
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