PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840008-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVCMOS/LVTTL
F
REQUENCY
S
YNTHESIZER
F
EATURES
• Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Output frequency range: 125MHz - 160MHz
• Crystal oscillator interface, 25MHz - 32MHz crystal
• VCO range: 500MHz - 640MHz
• RMS phase jitter (1.875MHz - 20MHz): 0.52ps (typical)
• Output skew: 150ps (maximum) (design target)
• Voltages supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS840008-01 is an 8 output LVCMOS/LVTTL
Synthesizer designed to generate 125MHz for
HiPerClockS™
Gigabit Ethernet applications and is a member of
the HiPerClocks
TM
family of high performance clock
solutions from ICS. The ICS840008-01 uses ICS’
3rd generation low phase noise VCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting
Gigabit Ethernet jitter requirements. The ICS840008-01 is
packaged in a small 24-pin SSOP package.
ICS
B
LOCK
D
IAGRAM
nPLL_SEL
Pulldown
P
IN
A
SSIGNMENT
V
DDO
nc
XTAL_OUT
XTAL_IN
V
DDA
OE
MR
nPLL_SEL
V
DD
nc
GND
nc
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
GND
Q2
Q3
V
DDO
Q4
Q5
GND
Q6
Q7
V
DDO
25MHz
XTAL_IN
1
Phase
Detector
VCO
500MHz -
640MHz
÷4
(fixed)
OSC
XTAL_OUT
0
8
8
Q0:Q7
÷20
(fixed)
ICS840008-01
24-Lead SSOP, 150MIL
3.9mm x 8.65mm x 1.5mm
package body
R Package
Top View
MR
Pulldown
OE
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840008AR-01
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840008-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVCMOS/LVTTL
F
REQUENCY
S
YNTHESIZER
Type
Power
Unused
Input
Power
Input
Input
Pullup
Description
Output supply pins.
No connect.
Crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Analog supply pin.
Output enable. LVCMOS/LVTTL interface levels
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the true outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and XTAL as the input to the dividers.
Pulldown When HIGH, selects XTAL. When LOW, selects PLL.
LVCMOS/LVTTL interface levels.
Core supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 13, 19
2, 10, 12
3,
4
5
6
7
Name
V
DDO
nc
XTAL_OUT,
XTAL_IN
V
DDA
OE
MR
8
9
nPLL_SEL
V
DD
Input
Power
11, 16, 22
GND
Power
Power supply ground.
14, 15, 17,
Q7, Q6, Q5,
Single-ended outputs.15
Ω
impedance.
18, 20, 21,
Q4, Q3, Q2,
Ouput
LVCMOS/LVTTL interface levels.
23, 24
Q1, Q0
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
V
DDO
= 3.63V
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.63V or 2.625V
V
DDO
= 1.89V
V
DDO
= 2.625V
V
DDO
= 1.89V
Test Conditions
Minimum
Typical
4
TBD
TBD
TBD
51
51
15
TBD
Maximum
Units
pF
pF
pF
pF
KΩ
KΩ
Ω
Ω
840001AR-01
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840008-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVCMOS/LVTTL
F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
73.1°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, V
DDO
= 3.3V±10%
OR
2.5V±5%
OR
1.8V±5%,
T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.97
2.97
2.97
2.375
1.71
Typical
3.3
3.3
3.3
2.5
1.8
65
5
4
Maximum
3.63
3.63
3.63
2.625
1.89
Units
V
V
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 2.5V±5%
OR
1.8V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
1.71
Typical
2.5
2.5
2.5
1.8
60
5
4
Maximum
2.625
2.625
2.625
1.89
Units
V
V
V
V
mA
mA
mA
840008AR-01
www.icst.com/products/hiperclocks.html
3
REV. A APRIL 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840008-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVCMOS/LVTTL
F
REQUENCY
S
YNTHESIZER
Test Conditions
OE, MR,
PLL_SEL
OE, MR,
PLL_SEL
MR,
nPLL_SEL
V
DD
= 3.3V ±10%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ±10%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ±10%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ±10%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ±10%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ±10%
V
DD
= 2.5V ± 5%
V
DDO
= 3.3V ± 10%
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 5%
V
DDO
= 3.3V±10% or 2.5V±5%
V
DDO
= 1.8V ± 5%
-5
-5
-150
-150
2.6
1.8
1.5
0.5
0.4
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.7
150
150
5
5
Units
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
I
IH
Input High Current
OE
MR,
nPLL_SEL
I
IL
Input Low Current
OE
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage: NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
25
Test Conditions
Minimum
Typical
Maximum
32
50
7
Units
MH z
MH z
Ω
pF
Fundamental
840001AR-01
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 7, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840008-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVCMOS/LVTTL
F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
125
TBD
Integration Range:
1.875MHz - 20MHz
20% to 80%
0.52
TBD
550
Typical
Maximum
160
Units
MHz
ps
ps
ms
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±10%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
Output Rise/Fall Time
t
sk(o)
t
jit(Ø)
t
L
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
Output Rise/Fall Time
Integration Range:
1.875MHz - 20MHz
20% to 80%
Test Conditions
Minimum
125
TBD
0.53
TBD
600
Typical
Maximum
160
Units
MHz
ps
ps
ms
ps
%
t
sk(o)
t
jit(Ø)
t
L
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, V
DDO
= 1.8V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
Output Rise/Fall Time
Integration Range:
1.875MHz - 20MHz
20% to 80%
Test Conditions
Minimum
125
TBD
0.49
TBD
630
Typical
Maximum
160
Units
MHz
ps
ps
ms
ps
%
t
sk(o)
t
jit(Ø)
t
L
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840008AR-01
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 7, 2005
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