R1RP0404D Series
4M High Speed SRAM (1-Mword
×
4-bit)
REJ03C0116-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RP0404D is a 4-Mbit high speed static RAM organized 1-Mword
×
4-bit. It has realized high speed
access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The R1RP0404D is packaged in 400-mil 32-pin SOJ for high
density surface mounting.
Features
•
Single 5.0 V supply: 5.0 V
±
10%
•
Access time 12 ns (max)
•
Completely static memory
No clock or timing strobe required
•
Equal access and cycle times
•
Directly TTL compatible
All inputs and outputs
•
Operating current: 130 mA (max)
•
TTL standby current: 40 mA (max)
•
CMOS standby current : 5 mA (max)
: 1.0 mA (max) (L-version)
•
Data retention current: 0.5 mA (max) (L-version)
•
Data retention voltage: 2.0 V (min) (L-version)
•
Center V
CC
and V
SS
type pin out
Rev.1.00, Mar.12.2004, page 1 of 11
R1RP0404D Series
Ordering Information
Type No.
R1RP0404DGE-2PR
R1RP0404DGE-2LR
Access time
12 ns
12 ns
Package
400-mil 32-pin plastic SOJ (32P0K)
Pin Arrangement
32-pin SOJ
A0
A1
A2
A3
A4
CS#
I/O1
V
CC
V
SS
I/O2
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
A18
A17
A16
A15
OE#
I/O4
V
SS
V
CC
I/O3
A14
A13
A12
A11
A10
NC
Pin Description
Pin name
A0 to A19
I/O1 to I/O4
CS#
OE#
WE#
V
CC
V
SS
NC
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
No connection
Rev.1.00, Mar.12.2004, page 2 of 11
R1RP0404D Series
Block Diagram
(LSB)
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(MSB)
I/O1
.
.
.
I/O4
Internal
voltage
generator
Row
decoder
1024-row
×
64-column
×
16-block
×
4-bit
(4,194,304 bits)
V
CC
V
SS
CS
Column I/O
Input
data
control
Column decoder
CS
WE#
CS#
A8 A9 A19 A17 A18 A15 A0 A2 A4 A16
(LSB)
(MSB)
OE#
CS
Rev.1.00, Mar.12.2004, page 3 of 11
R1RP0404D Series
Operation Table
CS#
H
L
L
L
L
OE#
×
H
L
H
L
WE#
×
H
H
L
L
Mode
Standby
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
I/O
High-Z
High-Z
D
OUT
D
IN
D
IN
Ref. cycle
Read cycle (1) to (3)
Write cycle (1)
Write cycle (2)
Note: H: V
IH
, L: V
IL
,
×:
V
IH
or V
IL
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
−0.5
to +7.0
−0.5*
to V
CC
+ 0.5*
1
2
Unit
V
V
W
°C
°C
°C
1.0
0 to +70
−55
to +125
−10
to +85
Notes: 1. V
T
(min) =
−2.0
V for pulse width (under shoot)
≤
6 ns.
2. V
T
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
≤
6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
*
V
SS
*
Input voltage
Notes: 1.
2.
3.
4.
V
IH
V
IL
3
4
Min
4.5
0
2.2
−0.5*
1
Typ
5.0
0
Max
5.5
0
V
CC
+ 0.5*
0.8
2
Unit
V
V
V
V
V
IL
(min) =
−2.0
V for pulse width (under shoot)
≤
6 ns.
V
IH
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
≤
6 ns.
The supply voltage with all V
CC
pins must be on the same level.
The supply voltage with all V
SS
pins must be on the same level.
Rev.1.00, Mar.12.2004, page 4 of 11
R1RP0404D Series
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5.0 V
±
10%, V
SS
= 0 V)
Parameter
Input leakage current
Output leakage current
Operation power supply current
Symbol
II
LI
I
II
LO
I
I
CC
Min
Max
2
2
130
Unit
µA
µA
mA
Test conditions
V
IN
= V
SS
to V
CC
V
IN
= V
SS
to V
CC
Min cycle
CS# = V
IL
, l
OUT
= 0 mA
Other inputs = V
IH
/V
IL
Min cycle, CS# = V
IH
,
Other inputs = V
IH
/V
IL
f = 0 MHz
V
CC
≥
CS#
≥
V
CC
−
0.2 V,
(1) 0 V
≤
V
IN
≤
0.2 V or
(2) V
CC
≥
V
IN
≥
V
CC
−
0.2 V
I
OL
= 8 mA
I
OH
=
−4
mA
Standby power supply current
I
SB
I
SB1
40
5
mA
mA
*
Output voltage
Note:
V
OL
V
OH
2.4
1
1.0*
0.4
1
V
V
1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Input capacitance*
Note:
1
1
Symbol
C
IN
C
I/O
Min
Max
6
8
Unit
pF
pF
Test conditions
V
IN
= 0 V
V
I/O
= 0 V
Input/output capacitance*
1. This parameter is sampled and not 100% tested.
Rev.1.00, Mar.12.2004, page 5 of 11