SIT2024AABS8-33N-8.000000D datasheet, PDF

SiT2024

Automotive AEC-Q100, Single-Chip, One-Output Clock Generator

The Smart Timing Choice

,

Features



Applications



AEC-Q100 with extended temperature range (-55°C to 125°C)

Frequencies between 1 MHz and 110 MHz accurate to 6 decimal

places

Supply voltage of 1.8V or 2.25V to 3.63V

Excellent total frequency stability as low as ±25 ppm

Industry best G-sensitivity of 0.1 PPB/G

Low power consumption of 3.8 mA typical at 1.8V

LVCMOS/LVTTL compatible output

5-pin SOT23-5 package: 2.9 x 2.8 mm x mm

RoHS and REACH compliant, Pb-free, Halogen-free and

Antimony-free

Automotive, extreme temperature and other high-rel electronics

Infotainment systems, collision detection devices, and in-vehicle

networking

Power train control

Electrical Specifications

Table 1. Electrical Characteristics

[1, 2]

Parameters

Output Frequency Range

Frequency Stability

Symbol

f

F_stab

Min.

1

-25

-30

-50

Operating Temperature Range

(ambient)

T_use

-40

-55

Supply Voltage

Current Consumption

Vdd

Idd

1.62

2.25

–

Duty Cycle

Rise/Fall Time

Output High Voltage

DC

Tr, Tf

VOH

45

–

90%

Typ.

–

1.8

–

4.0

3.8

–

1.5

1.3

–

Max.

110

+25

+30

+50

+105

+125

1.98

3.63

4.8

4.5

55

3

2.5

–

Unit

MHz

ppm

°C

V

mA

%

ns

Vdd

Condition

Refer to

Table 13 and Table 14

for a list supported frequencies

Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and

variations over operating temperature, rated power supply

voltage and load (15 pF ± 10%).

Frequency Range

Frequency Stability and Aging

Operating Temperature Range

Extended Industrial, AEC-Q100 Grade 2

Automotive, AEC-Q100 Grade 1

Extended Temperature, AEC-Q100

All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V

and 3.3V are supported.

No load condition, f = 20 MHz, Vdd = 2.25V to 3.63V

No load condition, f = 20 MHz, Vdd = 1.8V

All Vdds

Vdd = 2.25V - 3.63V, 20% - 80%

Vdd = 1.8V, 20% - 80%

IOH = -4 mA (Vdd = 3.0V or 3.3V)

IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)

IOH = -2 mA (Vdd = 1.8V)

IOL = 4 mA (Vdd = 3.0V or 3.3V)

IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)

IOL = 2 mA (Vdd = 1.8V)

Pin 1, OE

Pin 1, OE logic high or logic low

Measured from the time Vdd reaches 90% of final value

f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles

f = 75 MHz, 2.25V to 3.63V

f = 75 MHz, 1.8V

f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz

f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz

Supply Voltage and Current Consumption

LVCMOS Output Characteristics

Output Low Voltage

VOL

–

10%

Vdd

Input Characteristics

Input High Voltage

Input Low Voltage

Input Pull-up Impedence

Startup Time

Enable/Disable Time

RMS Period Jitter

RMS Phase Jitter (random)

VIH

VIL

Z_in

T_start

T_oe

T_jitt

T_phj

70%

–

100

–

1.6

1.9

0.5

1.3

–

30%

–

10

130

Jitter

2.5

3.0

–

ps

Vdd

k

ms

ns

Startup and Resume Timing

Notes:

1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.

2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at

25 °C temperature.

SiTime Corporation

Rev. 1.0

990 Almanor Avenue, Sunnyvale, CA 94085

(408) 328-4400

www.sitime.com

Revised May 28, 2015

SiT2024

Automotive AEC-Q100, Single-Chip, One-Output Clock Generator

The Smart Timing Choice

Table 2. Pin Description

1

2

3

4

5

Symbol

GND

NC

OE/ NC

VDD

OUT

Power

No Connect

Output

Enable

No Connect

Power

Output

Electrical ground

[4]

No connect

H

[3]

: specified frequency output

L: output is high impedance. Only output driver is disabled.

Any voltage between 0 and Vdd or Open

[3]

: Specified frequency

output. Pin 3 has no function.

Power supply voltage

Oscillator output

[4]

GND

1

Functionality

Top View

5

OUT

YXXXX

NC

2

OE/NC

3

4

VDD

Figure 1. Pin Assignments

Notes:

3. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option.

4. A capacitor of value 0.1 µF or higher between Vdd and GND is required.

N

Table 3. Absolute Maximum Limits

Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of

the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.

Parameter

Storage Temperature

Vdd

Electrostatic Discharge

Soldering Temperature (follow standard Pb free soldering guidelines)

Junction Temperature

[5]

Min.

-65

-0.5

–

Max.

150

4

2000

260

150

Unit

°C

V

°C

Note:

5. Exceeding this temperature for extended period of time may damage the device.

Table 4. Thermal Consideration

[6]

Package

SOT23-5



JA, 4 Layer Board

(°C/W)

421



JC, Bottom

(°C/W)

175

Note:

6. Refer to JESD51 for

JA

and

JC

definitions, and reference layout used to determine the

JA

and

JC

values in the above table.

Table 5. Maximum Operating Junction Temperature

[7]

Max Operating Temperature (ambient)

105°C

125°C

Maximum Operating Junction Temperature

115°C

135°C

Note:

7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.

Table 6. Environmental Compliance

Parameter

Mechanical Shock

Mechanical Vibration

Temperature Cycle

Solderability

Moisture Sensitivity Level

Condition/Test Method

MIL-STD-883F, Method 2002

MIL-STD-883F, Method 2007

JESD22, Method A104

MIL-STD-883F, Method 2003

MSL1 @ 260°C

Rev. 1.0

Page 2 of 11

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SiT2024

Automotive AEC-Q100, Single-Chip, One-Output Clock Generator

The Smart Timing Choice

Test Circuit and Waveform

[8]

Test

Point

Vout

Vdd

tr

5

4

0.1µF

Power

Supply

tf

80% Vdd

50%

20% Vdd

High Pulse

(TH)

Low Pulse

(TL)

Period

15 pF

(including probe

and fixture

capacitance)

1

2

3

1k

Ω

Vdd

OE/ST Function

Figure 2. Test Circuit

Note:

8. Duty Cycle is computed as Duty Cycle = TH/Period.

Figure 3. Waveform

Timing Diagrams

u

90% Vdd

Vdd

50% Vdd

Pin 4 Voltage

T_start

No Glitch

during start up

[9]

OE Voltage

T_oe

CLK Output

HZ

CLK Output

HZ

T_start: Time to start from power-off

T_oe: Time to re-enable the clock output

Figure 4. Startup Timing (OE Mode)

Vdd

OE Voltage

50% Vdd

Figure 5. OE Enable Timing (OE Mode Only)

T_oe

CLK Output

HZ

T_oe: Time to put the output in High Z mode

Figure 6. OE Disable Timing (OE Mode Only)

Note:

9. SiT2024 has “no runt” pulses and “no glitch” output during startup or resume.

Rev. 1.0

Page 3 of 11

www.sitime.com

SiT2024

Automotive AEC-Q100, Single-Chip, One-Output Clock Generator

The Smart Timing Choice

Performance Plots

[10]

DUT 1

DUT 6

DUT 2

DUT 7

DUT 3

DUT 8

DUT 4

DUT 9

DUT 5

DUT 10

1.8 V

2.5 V

2.8 V

3V

3.3 V

25

20

15

6.0

Frequency (ppm)

0

20

40

60

80

100

5.5

5.0

4.5

4.0

3.5

3.0

10

)

m

5

p

(

y

c

0

n

e

u

q

e

‐5

r

F

Idd (mA)

‐10

‐15

‐20

‐25

‐55

‐35

‐15

5

25

45

65

85

105

125

Tem per atur

(°C)

Temperature

e ( C)

Frequency (MHz)

Figure 7. Idd vs Frequency

Figure 8. Frequency vs Temperature

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

4.0

55

54

RMS period jitter (ps)

3.5

53

Duty cycle (%)

0

20

40

60

80

100

3.0

2.5

2.0

1.5

1.0

0.5

0.0

52

51

50

49

48

47

46

45

0

20

40

60

80

100

Frequency (MHz)

Figure 9. RMS Period Jitter vs Frequency

Figure 10. Duty Cycle vs Frequency

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

2.5

2.0

Rise time (ns)

Fall time (ns)

1.5

1.0

0.5

0.0

-55

-35

-15

5

25

45

65

85

105

125

0.0

-55

-35

-15

5

25

45

65

85

105

125

Temperature (°C)

Figure 11. 20%-80% Rise Time vs Temperature

Figure 12. 20%-80% Fall Time vs Temperature

Rev. 1.0

Page 4 of 11

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SiT2024

Automotive AEC-Q100, Single-Chip, One-Output Clock Generator

The Smart Timing Choice

Performance Plots

[10]

1.8 V

2

1.9

1.8

1.7

)

1.6

s

p

(

1.5

J

P

I

1.4

1.3

1.2

1.1

1

10

30

2.5 V

2.8 V

3.0 V

3.3 V

1

0.9

0.8

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

IPJ (ps)

50

70

90

110

)

0.7

s

p

(

J

P

I

0.6

0.5

0.4

0.3

10

30

50

70

90

110

Frequency (MHz)

Figure 14. RMS Integrated Phase Jitter Random

(12 kHz to 20 MHz) vs Frequency

[11]

Figure 15. RMS Integrated Phase Jitter Random

(900 kHz to 7.5 MHz) vs Frequency

[11]

Notes:

10. All plots are measured with 15 pF load at room temperature, unless otherwise stated.

11. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequencies below 40 MHz.

Rev. 1.0

Page 5 of 11

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Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	SiTime
Product Category	Standard Clock Oscillators
RoHS	Details
Frequency	8 MHz
Frequency Stability	30 PPM
Load Capacitance	-
Operating Supply Voltage	3.3 V
Supply Voltage - Min	1.62 V
Supply Voltage - Max	1.98 V
Output Format	LVCMOS
Termination Style	SMD/SMT
Package / Case	SOT-23-5
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 125 C
Length	2.9 mm
Width	2.8 mm
Height	1.25 mm
Packaging	Reel
Current Rating	4 mA
Type	Automotive
Duty Cycle - Max	55 %
Factory Pack Quantity	3000

SIT2024AABS8-33N-8.000000D

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