configured as 4x4Mx32. The SDRAM BGA is constructed
with two 16Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 17mm
by 23mm, BGA.
The WED3DL3216V is available in clock speeds
of 133MHz, 125MHz, and 100MHz. The range of
operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
The package and design provides performance
enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal
ground and power planes which reduces inductance
on the ground and power pins allowing for improved
decoupling and a reduction in system noise.
PIN CONFIGURATION
(Top view)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
CCQ
NC
NC
DQC
DQC
V
CCQ
DQC
DQC
V
CCQ
DQD
DQD
V
CCQ
DQD
DQD
NC
NC
V
CCQ
1
2
NC
NC
NC
NC
DQC
DQC
DQC
DQC
V
CC
DQD
DQD
DQD
DQD
NC
A6
NC
NC
2
3
4
BA0
NC
A12
CAS#
BA1
V
CC
V
SS
NC
V
SS
CE#
V
SS
RAS#
DQMC NC
V
SS
CKE
NC
V
CC
V
SS
CK
DQMD NC
V
SS
WE#
V
SS
A1
V
SS
NC
A5
NC
3
A0
V
CC
A4
NC
4
5
A10
A11
A9
V
SS
V
SS
V
SS
DQMB
V
SS
NC
V
SS
DQMA
V
SS
V
SS
V
SS
NC
A3
NC
5
6
A7
NC
A8
NC
DQB
DQB
DQB
DQB
V
CC
DQA
DQA
DQA
DQA
NC
A2
NC
NC
6
7
V
CCQ
NC
NC
DQB
DQB
V
CCQ
DQB
DQB
V
CCQ
DQA
DQA
V
CCQ
DQA
DQA
NC
NC
V
CCQ
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
PIN DESCRIPTION
A0 – A12
BA0-1
DQ
CK
CKE
DQM
RAS#
CAS#
CE#
V
CC
V
CCQ
V
SS
Address Bus
Bank Select Addresses
Data Bus
Clock
Clock Enable
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Chip Enable
Power Supply pins, 3.3V
Data Bus Power Supply pins,3.3V
Ground pins
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
16MX32 SDRAM BLOCK DIAGRAM
ADDR0-12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
DQMA
DQMB
CE#
RAS#
CAS#
WE#
CK
CKE
BA0
BA1
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK
CKE
DQ0-7
DQ8-15
WED3DL3216V
DQA
DQB
DQ0-31
DQ0-7
DQ8-15
DQC
DQD
DQMC
DQMD
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
I
NPUT
/O
UTPUT
F
UNCTIONAL
D
ESCRIPTION
Symbol
CK
CKE
CE#
RAS#, CAS#,
WE#
BA0, BA1
Type
Input
Input
Input
Input
Input
Signal
Pulse
Level
Pulse
Pulse
Level
WED3DL3216V
A0-12
Input
Level
DQ
Input/Output
Level
Polarity
Function
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
Active High
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
Active Low
DQM.
When sampled at the positive rising edge of the clock, CAS#, RAS# and WE# define the
Active Low
operation to be executed by the SDRAM
−
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-12 defines the row address (RA0-12) when sampled
at the rising clock edge.
During a Read or Write command cycle, A0-9 defines the column address (CA0-9) when
sampled at the rising edge of the clock. In addition to the row address, A10/AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,
−
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0, BA1. If A10/AP is low, than BA0, BA1 is used to define which bank to precharge.
−
Data Input/Output are multiplexed on the same pins
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
CC
/V
CCQ
V
IN
V
OUT
T
OPR
T
TSG
P
D
I
OS
Min
-1.0
-1.0
-1.0
-0
-55
—
—
Max
+4.6
+4.6
+4.6
+70
+125
1.5
50
Units
V
V
V
°C
°C
W
mA
* Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
RECOMMENDED DC OPERATING CONDITIONS
(V
OLTAGE
R
EFERENCED TO
: V
SS
= 0V, 0°C ≤ T
A
≤ 70°C; C
OMMERCIAL OR
T
A
= -40°C
TO
+85°C; I
NDUSTRIAL
)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
(I
OH
= -2mA)
Output Low Voltage
(I
OL
= 2mA)
Input Leakage Voltage
Output Leakage
Voltage
Symbol
V
CC
/V
CCQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
—
-5
-5
Typ
3.3
3.0
—
—
—
—
—
Max
3.6
V
CC
+0.3
0.8
—
0.4
5
5
Unit
V
V
V
V
V
µA
µA
Parameter
Input Capacitance
Input/Output Capacitance (DQ)
WED3DL3216V
CAPACITANCE
(T
A
= 25°C, f = 1MH
Z
, V
CC
= 3.3V)
Symbol
C
I1
C
OUT
Max
4
5
Unit
pF
pF
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, T
A
= 0°C
TO
70°C; C
OMMERCIAL OR
TA = -40°C
TO
+85°C; I
NDUSTRIAL
)
Parameter
Operating Current (One Bank Active)
Operating Current (Burst Mode)
1
Precharge Standby Current
in Power Down Mode
1
Symbol
I
CC1
I
CC4
I
CC2P
I
CC2PS
I
CC1N
Conditions
Burst Length = 1, t
RC
≥ t
RC
(min), I
OL
= 0mA
Page Burst, 4 banks active, t
CCD
= 2 clocks
CKE ≤ V
IL
(max), t
CC
= 15ns
CKE, CK ≤ V
IL
(max), t
CC
= ∞, Inputs Stable
CKE = V
IH
, t
CC
= 15ns
Input Change one time every 30ns
CKE ≥ V
IH
(min), t
CC
= ∞
No Input Change
CKE ≤ V
IL
(max), t
CC
= 15ns
CKE ≤ V
IL
(max), t
CC
= ∞
CKE = V
IH
, t
CC
= 15ns
Input Change one time every 30ns
CKE ≥ V
IH
(min), t
CC
= ∞, No Input Change
t
RC
≥ t
RC
(min)
CKE ≤ 0.2V
-7
300
300
2
2
140
70
12
12
60
50
600
6.5
-8
280
280
2
2
140
70
12
12
60
50
570
6.5
-10
260
260
2
2
140
70
12
12
60
50
550
6.5
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Precharge Standby Current
in Non-Power Down Mode
I
CC1NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC5
I
CC6
Precharge Standby Current
in Power Down Mode
Active Standby Current in
Non-Power Down Mode
(One Bank Active)
Refresh Current
2
Self Refresh Current
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
SDRAM AC CHARACTERISTICS
Parameter
CL = 3
CL = 2
Clock to valid Output delay
1,2
Output Data Hold Time
2
Clock HIGH Pulse Width
3
Clock LOW Pulse Width
3
Input Setup Time
3
Input Hold Time
3
CK to Output Low-Z
2
CK to Output High-Z
Row Active to Row Active Delay
4
RAS to CAS Delay
4
Row Precharge Time
4
Row Active Time
4
Row Cycle Time - Operation
4
Row Cycle Time - Auto Refresh
4,8
Last Data in to New Column Address Delay
5
Last Data in to Row Precharge
5
Last Data in to Burst Stop
5
Column Address to Column Address Delay
6
Number of Valid OutputData
7
Symbol
t
CC
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
t
RRD
t
RCD
t
RP
t
RAS
t
RC
t
RFC
t
CDL
t
RDL
t
BDL
t
CCD
133MH
Z
Min
7
7.5
3
2.5
2.5
1.5
0.8
2
5.4
24
24
24
60
90
90
1
1
1
1.5
2
1
20
20
20
50
70
70
1
1
1
1.5
2
1
Max
1000
1000
5.4
125MH
Z
Min
8
10
3
3
3
2
1
2
6
Max
1000
1000
6
WED3DL3216V
100MH
Z
Min
10
12
3
3
3
2
1
2
7
20
20
20
50
80
80
1
1
1
1.5
2
2
Max
1000
1000
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
ea
10,000
10,000
10,000
NOTES:
1.
Parameters depend on programmed CAS latency.
2.
If clock rise time is longer than 1ns (t
RISE
/2 -0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If t
RISE
or t
FALL
are longer than 1ns. [(t
RISE
= t
FALL
)/2] - 1ns should be added to the parameter.
4.
The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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