PIC18(L)F26/45/46/55/56K42
PIC18(L)F26/45/46/55/56K42 Family
Silicon Errata and Data Sheet Clarification
The PIC18(L)F26/45/46/55/56K42 family devices that
you have received conform functionally to the current
Device Data Sheet (DS40001919B), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18(L)F26/45/46/55/56K42
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon
revision (A2).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
For MPLAB X IDE, select
Window > Dashboard
and click the
Refresh Debug Tool Status
icon
(
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
5.
Data Sheet clarifications and corrections start on
page
6,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate website
(www.microchip.com).
The
DEVREV
values
for
the
various
PIC18(L)F26/45/46/55/56K42 silicon revisions are
shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device ID<13:0>
(1), (2)
6C60h
6C20h
6C00h
6BC0h
6BA0h
6DA0h
6D60h
6D40h
6D00h
6CE0h
Revision ID for Silicon Revision
A1
A2
A002
A002
A002
A002
A002
A002
A002
A002
A002
A002
Part Number
PIC18F26K42
PIC18F45K42
PIC18F46K42
PIC18F55K42
PIC18F56K42
PIC18LF26K42
PIC18LF45K42
PIC18LF46K42
PIC18LF55K42
PIC18LF56K42
Note 1:
2:
A001
A001
A001
A001
A001
A001
A001
A001
A001
A001
The Revision ID is located in addresses 3FFFFCh-3FFFFDh and Device ID is located in addresses
3FFFFEh-3FFFFFh.
Refer to the
“PIC18(L)F26/45/46/55/56K42 Memory Programming Specification”
(DS40001886) for
detailed information on Device and Revision IDs for your specific device.
2017-2018 Microchip Technology Inc.
DS80000745D-page 1
PIC18(L)F26/45/46/55/56K42
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
SMBus 2.0
Item
No.
1.1
1.2
1.3
Affected Revisions
(1)
Issue Summary
A1
SMBus 2.0 logic levels.
SMBus 3.0 logic levels.
V
DDMIN
for LF devices is 2.0V.
MFINTOSC clock sources into the
SMT are not functional.
DMA reads from Data EEPROM
does not operate.
DMA transfers may not work when
CPU is in Doze mode.
BRGS Select feature not functional
in DALI mode.
Stop Bit interrupt flag functionality
not available.
WRERR bit cannot be cleared in
hardware after being set once.
Window violation occurs when
WWDT operated in Doze mode.
Low-power Sleep mode does not
operate at 3.1v<V
DD
<3.3v.
The 12-bit ADC shorts briefly at the
beginning of the ADC conversion
stage.
The ADC
2
does not trigger the
second conversion when operated
in non-continuous double-sampling
Burst Average mode.
X
X
X
X
X
X
X
X
X
X
X
X
X
A2
Electrical
Specifications
SMBus 3.0
Min V
DD
Specification for LF
Devices
MFINTOSC Clock
Sources into SMT
DMA Reads from
Data EEPROM
DMA in Doze Mode
Signal
Measurement
Timer (SMT)
2.1
3.1
3.2
4.1
4.2
5.1
6.1
7.1
8.1
X
X
X
X
DMA
X
X
UART
UART
NVM Control
WWDT
Power-Saving
Operation Modes
BRGS Select
Stop Bit Interrupt
Flag
WRERR Bit
Functionality
WWDT Operation in
Doze Mode
Low-Power Sleep
Mode
ADC Conversion
ADC2
Burst Average Mode
Double Sampling
Note 1:
8.2
X
X
Only those issues indicated in the last column apply to the current silicon revision.
2017-2018 Microchip Technology Inc.
DS80000745D-page 2
PIC18(L)F26/45/46/55/56K42
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
2. Module: Signal Measurement Timer
(SMT)
2.1 MFINTOSC Clock Sources into SMT
The Signal Measurement Timer does not
operate when MFINTOSC is selected as the
clock source (i.e. CSEL =
0b100
and
0b101).
Work around
The MFINTOSC does not start up automatically.
User software needs to manually enable the
MFINTOSC by setting the MFOEN bit in the
OSCCEN register. The MFINTOSC will remain
enabled as long as MFOEN bit is set.
Affected Silicon Revisions
A1
X
A2
X
1. Module: Electrical Specifications
1.1 SMBus 2.0
The SMBus 2.0 V
IL
specification (Parameter
D304) at 125°C is 0.7V.
Work around
None.
Affected Silicon Revisions
A1
X
1.2 SMBus 3.0
The SMBus 3.0 V
IL
specification (Parameter
D305) is temperature and V
DD
dependent. Refer
to the table below.
Temperature
-40°C
-40°C
25°C
25°C
85°C
85°C
125°C
125°C
V
DD
1.8V
5.5V
1.8V
5.5V
1.8V
5.5V
1.8V
5.5V
D305 SMBus 3.0 V
IL
Specification
0.6V
0.8V
0.6V
0.8V
0.6V
0.7V
0.5V
0.7V
A2
3. Module: DMA
3.1 DMA Reads from Data EEPROM
The DMA modules do not operate when CPU is
in Doze mode (DOZEN =
1
in CPUDOZE
register).
Work around
None. NVMCON reads work as described.
Affected Silicon Revisions
A1
X
3.2 DMA in Doze Mode
When the CPU is operated in Doze mode, DMA
transfers may not work as expected.
Work around
None.
Affected Silicon Revisions
A1
X
A2
X
A2
Work around
None.
Affected Silicon Revisions
A1
X
A2
X
1.3 Min VDD Specification for LF Devices
V
DDMIN
for LF devices (Parameter D002) is
2.0V.
Work around
None.
Affected Silicon Revisions
A1
X
A2
X
2017-2018 Microchip Technology Inc.
DS80000745D-page 3
PIC18(L)F26/45/46/55/56K42
4. Module: UART
4.1 Baud Rate Generator Speed Select
The Baud Rate Generator Speed Select feature
(BRGS bit in the UxCON0 register) in DALI
mode is not functional. The Baud Rate
Generator always operates at normal speed
with 16 baud clocks per bit in DALI mode.
Work around
None.
Affected Silicon Revisions
A1
A2
X
4.2 Stop Bit Interrupt Flag
Stop Bit interrupt flag functionality is not
available in the CERIF bit in revision A1.
Work around
Use Timer2 with HLT and connect the UART RX
port to the timer Reset trigger. Set the time-out
period to the desired Stop bit time (for DALI
mode, this is equivalent to two Stop bits at 1200
baud = 1.66 ms). When the Stop bit is received,
the timer times out notifying end of data.
Affected Silicon Revisions
A1
X
A2
a)
6. Module: WWDT
6.1 WWDT Operation in Doze Mode
When the
CLRWDT
instruction is issued in Doze
mode, a window violation error occurs in WWDT
even though the window is open and armed.
Work around
Do not operate the WWDT in Doze mode.
Affected Silicon Revisions
A1
X
A2
X
7. Module: Power-Saving Operation Modes
7.1 Low-Power Sleep Mode in F Devices
The F device resets when waking up from Sleep
while in Low-Power mode (VREGPM =
1
in
VREGCON register) at 3.1V < V
DD
< 3.3V.
Work around
If wake-up from Sleep is needed at 3.1V < V
DD
< 3.3V, operate the F device in Normal Power
mode (VREGPM =
0).
If wake-up from Sleep is needed at 3.1V < V
DD
< 3.3V, enable the Fixed Voltage Reference (EN
=
1
in FVRCON register). This increases the
current in Sleep mode by typically 7 µA.
Affected Silicon Revisions
A1
A2
X
b)
5. Module: NVM Control
5.1 WRERR Bit Functionality
When a Reset is issued while an NVM high-
voltage operation is in progress, the WRERR bit
in the NVMCON1 register is set as expected.
After clearing the WRERR bit, if a Reset
reoccurs, the WRERR bit is set again regardless
of whether an NVM operation is in progress or
not.
Work around
None.
Affected Silicon Revisions
A1
X
A2
X
X
2017-2018 Microchip Technology Inc.
DS80000745D-page 4
PIC18(L)F26/45/46/55/56K42
8. Module: ADC
2
8.1 ADC Conversion
At the very beginning of the ADC conversion,
the input signal may briefly be pulled to ground,
which in turn may take some charge out of the
internal sample and hold capacitor. The problem
is more pronounced on inputs with an imped-
ance greater than 1K ohm.
This issue will be seen when sampling the
following internal channel inputs: FVR, DAC,
and Temperature Indicator and when sampling
external sources on an analog pin, including the
CVD.
Work around
a)
When sampling the internal channel inputs,
FVR, DAC, and Temperature Indicator, increase
the minimum TAD time to 4
s
to increase
accuracy.
When sampling an external source through an
analog pin, keep the input impedance below 1K
ohm.
When using the ADC in CVD mode, there is no
work around.
Affected Silicon Revisions
A1
X
A2
8.2 Burst Average Mode Double Sampling
When the ADC
2
is operated in Burst Average
mode (MD = 0b011 in ADCON2 register) while
enabling non-continuous operation and double-
sampling (CONT =
0
in the ADCON0 register
and DSEN =
1
in the ADCON1 register), the
value in the ADCNT register does not increment
beyond 0b1 toward the value in the ADRPT
register.
Work around
When operating the ADC
2
in Burst Average
mode with double-sampling, enable continuous
operation of the module (CONT =
1
in the
ADCON0 register) and set the stop-on-interrupt
bit (SOI bit in the ADCON3 register). After the
interrupt occurs, perform appropriate threshold
calculations in the software and retrigger ADC
2
as necessary.
If the CPU is in Low-Power Sleep mode, alterna-
tively the ADC
2
in non-continuous Burst
Average mode can be operated with single ADC
conversion (DSEN =
0
in the ADCON1 register)
compromising noise immunity for lower power
consumption by preventing the device from
waking up to perform threshold calculations in
the software.
Affected Silicon Revisions
A1
X
A2
X
b)
c)
2017-2018 Microchip Technology Inc.
DS80000745D-page 5
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