WM8195
14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
DESCRIPTION
The WM8195 is a 14-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset Adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 14-bit
analogue-to-digital converter. The digital output data is
available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed
format, with no missing codes.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. Alternatively an external reference level may be
applied. ADC references are generated internally, ensuring
optimum performance from the device.
Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the WM8195 typically
only consumes 210mW when operating from a single 5V
supply and less than 20µA when in power down mode.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
14-bit ADC
No missing codes guaranteed
12MSPS conversion rate
Low power – 210mW typical
5V single supply or 5V/3.3V dual supply operation
Single or 3 channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
14-bit parallel or 8, 7 or 4-bit wide multiplexed data output
formats
Internally generated voltage references
48-pin TQFP package
Serial or parallel control interface
APPLICATIONS
•
•
•
•
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
BLOCK DIAGRAM
VRLC/VBIAS
VSMP
MCLK
AVDD1-2
DVDD1-3
VRT VRX VRB
w
CL
R
S
V
S
TIMING CONTROL
R
G
B
M
U
X
8
WM8195
VREF/BIAS
OFFSET
DAC
+
PGA
8
OEB
+
I/P SIGNAL
POLARITY
ADJUST
M
U
X
14-
BIT
ADC
DATA
I/O
PORT
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]
OP[10]
OP[11]
OP[12]
OP[13]/SDO
RINP
RLC
M
U
X
CDS
R
G
B
M
U
X
GINP
RLC
CDS
8
+
OFFSET
DAC
PGA
8
+
I/P SIGNAL
POLARITY
ADJUST
BINP
RLC
CDS
8
+
OFFSET
DAC
PGA
8
+
I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
NRESET
RLC
DAC
4
AGND1-6
DGND1-5
WOLFSON MICROELECTRONICS LTD
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Advanced Information September 2002, Rev 2.0
Copyright
2002
Wolfson Microelectronics Ltd.
WM8195
PIN CONFIGURATION
OP[13]/SDO
OP[12]
NRESET
NC
DGND5
VRB
AGND6
AGND5
AVDD2
AVDD1
OP[11]
VRT
Advanced Information
ORDERING INFORMATION
DEVICE
XWM8195CFT
TEMP. RANGE
0 to 70°C
PACKAGE
48-pin TQFP
1mm thick body
VRX
VRLC/VBIAS
AGND1
BINP
AGND2
GINP
AGND3
RINP
AGND4
DVDD1
OEB
SEN/STB
1
2
3
4
5
6
7
8
9
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
DGND4
DVDD3
OP[10]
OP[9]
OP[8]
OP[7]
DGND3
OP[6]
OP[5]
OP[4]
OP[3]
DGND2
10
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
SDI/DNA
SCK/RNW
VSMP
RLC/ACYC
MCLK
DGND1
PIN DESCRIPTION
PIN
1
2
NAME
VRX
VRLC/VBIAS
TYPE
Analogue output
Analogue I/O
DESCRIPTION
Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
Analogue ground (0V).
Blue channel input video.
Analogue ground (0V).
Green channel input video.
Analogue ground (0V).
Red channel input video.
Analogue ground (0V).
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Serial interface: enable pulse, active high
Parallel interface: strobe, active low
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
13
14
SDI/DNA
SCK/RNW
Digital input
Digital input
Serial interface: serial input data signal
Serial interface: serial clock signal
Parallel interface:
High = data, Low = address
Parallel interface:
High: OP[13:6] is output bus.
Low: OP[13:6] is input bus (Hi-Z).
ACYC autocycles between R, G, B
inputs when in Line-by-Line mode.
3
4
5
6
7
8
9
10
11
12
AGND1
BINP
AGND2
GINP
AGND3
RINP
AGND4
DVDD1
OEB
SEN/STB
Supply
Analogue input
Supply
Analogue input
Supply
Analogue input
Supply
Supply
Digital input
Digital input
DVDD2
OP[0]
OP[1]
OP[2]
NC
NC
15
16
VSMP
RLC/ACYC
Digital input
Digital input
Video sample synchronisation pulse.
RLC (active high) selects reset level
clamp on a pixel-by-pixel basis – tie high
if used on every pixel.
17
18
19
20
MCLK
DGND1
NC
NC
Digital input
Supply
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
No connection.
No connection.
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AI Rev 2.0 September 2002
2
Advanced Information
PIN
21
22
23
NAME
OP[0]
OP[1]
OP[2]
TYPE
Digital output
Digital output
Digital output
DESCRIPTION
WM8195
Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes:
Hi-Z: when OEB = 1.
14-bit output: 14-bit data is output on OP[13:0].
8-bit multiplexed output: data is output on OP[13:6] at 2
∗
ADC conversion rate.
7-bit multiplexed output: data is output on OP[13:6] at 2
∗
ADC conversion rate.
4-bit multiplexed output: data is output on OP[13:10] at 4
∗
ADC conversion rate.
See Output Formats section in Device Description for further details.
Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0,
and SEN/STB = 0.
Output 8-bit: register read back data is output in parallel on OP[13:6] when
SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.
Digital I/O supply (3.3V/5V).
Digital ground (0V).
See pins 21 to 23 for details.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DVDD2
DGND2
OP[3]
OP[4]
OP[5]
OP[6]
DGND3
OP[7]
OP[8]
OP[9]
OP[10]
DVDD3
DGND4
OP[11]
OP[12]
OP[13]/SDO
Supply
Supply
Digital output
Digital output
Digital output
Digital I/O
Supply
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Supply
Digital I/O
Digital I/O
Digital I/O
Digital ground (0V).
See pins 21 to 23 for details.
Digital I/O supply (3.3V/5V).
Digital ground (0V).
See pins 21 to 23 for details.
If the device has been configured to use the serial interface, pin OP[13]/SDO may
be used to output register read-back data when OEB = 0 and SEN has been
pulsed high.
See Serial Interface sections in Device Description for further details.
Digital ground (0V).
No connection.
Reset input, active low. This signal forces a reset of all internal registers and selects
whether the serial or parallel control interface is used. See pin SEN/STB.
Analogue supply (5V).
Analogue supply (5V).
Analogue ground (0V).
Analogue ground (0V).
Lower reference voltage. This pin must be capacitively decoupled to AGND.
Lower reference voltage. This pin must be capacitively decoupled to AGND.
40
41
42
43
44
45
46
47
48
DGND5
NC
NRESET
AVDD1
AVDD2
AGND5
AGND6
VRB
VRT
Supply
Digital input
Supply
Supply
Supply
Supply
Analogue output
Analogue output
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AI Rev 2.0 September 2002
3
WM8195
ABSOLUTE MAXIMUM RATINGS
Advanced Information
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
Analogue supply voltages: AVDD1, 2
Digital supply voltages: DVDD1
−
3
Digital grounds: DGND1
−
5
Analogue grounds: AGND1
−
6
Digital inputs, digital outputs and digital I/O pins
Analogue inputs (RINP, GINP, BINP)
Other pins
Operating temperature range: T
A
Storage temperature
Package body temperature (soldering, 10 seconds)
Package body temperature (soldering, 2 minutes)
Notes:
1.
2.
MIN
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
0
°
C
-65
°
C
MAX
GND + 7V
GND + 7V
GND + 0.3V
GND + 0.3V
DVDD2 + 0.3V
AVDD + 0.3V
AVDD + 0.3V
+70
°
C
+150
°
C
+240
°
C
+183°C
GND denotes the voltage of any ground pin.
AGND1
−
6 and DGND1
−
5 pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
Operating temperature range
Analogue supply voltage
Digital core supply voltage
Digital I/O supply voltage
5V I/O
3.3V I/O
SYMBOL
T
A
AVDD1, 2
DVDD1
DVDD2, 3
DVDD2, 3
MIN
0
4.75
4.75
4.75
2.97
5.0
5.0
5.0
3.3
TYP
MAX
70
5.25
5.25
5.25
3.63
UNITS
°C
V
V
V
V
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AI Rev 2.0 September 2002
4
Advanced Information
WM8195
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70°C, MCLK = 24MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions)
NO MISSING CODES GUARANTEED
Conversion rate
Full-scale input voltage range
(see Note 1)
Input signal limits (see Note 2)
Full-scale transition error
Zero-scale transition error
Differential non-linearity
Integral non-linearity
Channel to channel gain matching
Total output noise
References
Upper reference voltage
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLC deviation
Offset DAC, Monotonicity Guaranteed
Resolution
Differential non-linearity
Integral non-linearity
Step size
Output voltage
Notes:
1.
2.
Full-scale input voltage
denotes the maximum amplitude of the input signal at the specified gain.
Input signal limits
are the limits within which the full-scale input voltage signal must lie.
AI Rev 2.0 September 2002
5
Code 00(hex)
Code FF(hex)
DNL
INL
8
0.1
0.25
2.04
-260
+260
0.5
1
bits
LSB
LSB
mV/step
mV
mV
V
RLCSTEP
V
RLCSTEP
V
RLCBOT
V
RLCBOT
V
RLCTOP
V
RLCTOP
-50
VRLC = 0 to AVDD
4
0.25
0.17
0.39
0.26
4.16
2.81
+50
50
5
2
1
Ω
mA
Ω
µA
bits
V/step
V/step
V
V
V
V
mV
VRT
VRB
VRX
V
RTB
1.4
2.85
1.35
1.65
1.5
1
1.6
V
V
V
V
Ω
Min Gain
Max Gain
DNL
INL
V
IN
Gain = 0dB;
PGA[7:0] = 4B(hex)
Gain = 0dB;
PGA[7:0] = 4B(hex)
Max Gain
Min Gain
0
20
20
1.25
8
1
1
3
12
0.4
4.08
AVDD
MSPS
Vp-p
Vp-p
V
mV
mV
LSB
LSB
%
LSB rms
LSB rms
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