NB6L611
2.5V / 3.3V 1:2 Differential
LVPECL Clock / Data Fanout
Buffer
Multi−Level Inputs with Internal Termination
Description
http://onsemi.com
MARKING
DIAGRAM*
1
QFN−16
MN SUFFIX
CASE 485G
16
NB6L
611
ALYWG
G
The NB6L611 is a differential 1:2 clock or data fanout buffer. The
differential inputs incorporate internal 50
W
termination resistors that
are accessed through the VTD pins and will accept LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels.
T h e V
R E FA C
r e f e r e n c e o u t p u t c a n b e u s e d t o r e b i a s
capacitor−coupled differential or single−ended input signals. When
used, decouple V
REFAC
with a 0.01
mF
capacitor and limit current
sourcing or sinking to 0.5 mA. When used, decouple V
REFAC
with a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
REFAC
output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L611 is a member of the ECLinPS MAX™ family of high
performance clock and data management products.
Features
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTD
D
D
VTD
VREFAC
Q0
Q1
Q1
•
•
•
•
•
•
•
•
•
•
Input Clock Frequency > 4.0 GHz
280 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential LVPECL Outputs, 780 mV Amplitude, typical
LVPECL Operating Range: V
CC
= 2.375 V to 3.63 V with V
EE
= 0 V
NECL Operating Range: V
CC
= 0 V with V
EE
=
−2.375
V to
−3.63
V
Internal Input Termination Resistors, 50
W
V
REFAC
Reference Output Voltage
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
•
−40°C
to +85°C Ambient Operating Temperature
•
These are Pb−Free Devices
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 4
1
Publication Order Number:
NB6L611/D
NB6L611
V
CC
16
VTD
D
D
VTD
1
2
NB6L611
3
4
5
6
7
8
V
CC
10
9
Q1
Q1
V
EE
V
EE
15
14
V
CC
13
12
11
Q0
Q0
Exposed Pad (EP)
V
CC
V
REFAC
V
EE
Figure 2. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTD
D
I/O
−
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
Internal 50
W
Termination Pin for D input.
Noninverted Differential Input. Note1. Internal 50
W
Resistor to Termination Pin, VTD.
Description
3
D
Inverted Differential Input. Note 1. Internal 50
W
Resistor to Termination Pin, VTD.
4
5
6
7
8
9
10
11
12
13
14
15
16
−
VTD
V
CC
V
REFAC
V
EE
V
CC
Q1
Q1
Q0
Q0
V
CC
V
EE
V
EE
V
CC
EP
Internal 50
W
Termination Pin for D input.
Positive Supply Voltage
Output Reference Voltage for direct or capacitor coupled inputs
−
−
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
−
−
−
−
−
Negative Supply Voltage
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
−
2.0 V.
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
−
2.0 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
−
2.0 V.
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
−
2.0 V.
Positive Supply Voltage
Negative Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and
if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation.
2. All V
CC
and V
EE
pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2
NB6L611
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
16−QFN
Oxygen Index: 28 to 34
Value
> 2 kV
> 200V
Level 1
UL 94 V−0 @ 0.125 in
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
IO
V
INPP
I
IN
I
OUT
I
VREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input/Output Voltage
Negative Input/Output Voltage
Differential Input Voltage |D
−
D|
Input Current Through R
T
(50
W
Resistor)
Output Current (LVPECL Output)
V
REFAC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder Pb−Free
0 lfpm
500 lfpm
(Note 3)
QFN−16
QFN−16
QFN−16
16 QFN
Static
Surge
Continuous
Surge
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
−0.5
v
V
Io
v
V
CC
+ 0.5
+0.5
w
V
Io
w
V
EE
−
0.5
Condition 2
Rating
4.0
−4.0
4.5
−4.5
V
CC
−V
EE
45
80
50
100
$2.0
−40
to +85
−65
to +150
42
35
4
265
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB6L611
Table 4. DC CHARACTERISTICS, Multi−Level Inputs
V
CC
= 2.375 V to 3.63 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
=
−2.375
V to
−3.63
V, T
A
=
−40°C
to +85°C
Symbol
POWER SUPPLY CURRENT
I
CC
V
OH
Power Supply Current (Inputs and Outputs Open)
30
45
60
mA
Characteristic
Min
Typ
Max
Unit
LVPECL OUTPUTS
(Notes 4 and 5)
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
−
1075
2225
1425
V
CC
−
1875
1475
675
V
CC
−
950
2350
1550
V
CC
−
1725
1575
775
V
CC
−
825
2475
1675
V
CC
−
1625
1675
875
mV
V
OL
Output LOW Voltage
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(see Figures 9 and 10) (Note 6)
V
th
V
IH
V
IL
V
ISE
V
REFAC
V
REFAC
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
R
TIN
Output Reference Voltage (V
CC
w
25 V)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input Common Mode Range (Differential Configuration) (Note9)
Input HIGH Current D/D, (VTD/VTD Open)
Input LOW Current D/D, (VTD/VTD Open)
V
CC
– 1.525
V
EE
+ 1200
V
EE
V
EE
+ 150
V
EE
+ 950
−150
−150
V
CC
– 1.425
V
CC
– 1.325
V
CC
V
CC
−
150
V
CC
−V
EE
V
CC
−
75
150
150
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figures 11, 12 and 13) (Note 8)
mV
mV
mV
mV
mA
mA
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Single−ended Input Voltage Amplitude (V
IH
−
V
IL
)
V
EE
+ 1050
V
th
+ 150
V
EE
300
V
CC
−
150
V
CC
V
th
−
150
V
CC
−V
EE
mV
mV
mV
mV
TERMINATION RESISTORS
Internal Input Termination Resistor (Measured from D to VTD)
40
50
60
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50
W
to V
CC
−
2.0 V for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
9. V
CMR
minimum varies 1:1 with V
EE
, V
CMR
maximum varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the
differential input signal.
http://onsemi.com
4
NB6L611
Table 5. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.63 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
=
−2.375
V to
−3.63
V,
T
A
=
−40°C
to +85°C; (Note 10)
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPP
)
(Note 14) (See Figure 3)
t
PD
t
SKEW
Propagation Delay
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
RMS Random Clock Jitter (Note 13)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
Output Rise/Fall Times @ 0.5 GHz (20%
−
80%)
Q, Q
f
in
≤
4.0 GHz
f
in
≤
4.0 GHz
150
100
40
f
in
≤
1.5 GHz
f
in
= 2.0 GHz
f
in
= 3.0 GHz
f
in
= 4.0 GHz
D to Q
Min
725
520
320
170
225
Typ
780
680
500
400
280
3
50
0.2
375
15
15
80
60
0.5
V
CC
−
V
EE
170
Max
Unit
mV
ps
ps
t
DC
t
JITTER
V
INPP
t
r
,t
f
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
−
2.0 V. Input edge rates
40 ps (20%
−
80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw
−
and T
pw
+ @ 0.5GHz.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Input and output voltage swing is a single−ended measurement operating in differential mode.
V
OUTPP
OUTPUT VOLTAGE AMPLITUDE (mV)
(TYPICAL)
800
700
600
500
400
300
200
100
0
0
1
2
3
4
f
out
, CLOCK OUTPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus Output
Frequency at Ambient Temperature (Typical)
http://onsemi.com
5
京公网安备 11010802033920号
EEWORLD
