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A54SX16P-2PQG208

Description
FPGA - Field Programmable Gate Array SX
CategoryProgrammable logic devices    Programmable logic   
File Size459KB,65 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
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A54SX16P-2PQG208 Overview

FPGA - Field Programmable Gate Array SX

A54SX16P-2PQG208 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrosemi
package instructionFQFP, QFP208,1.2SQ,20
Reach Compliance Codecompliant
Other featuresCAN ALSO BE OPERATED AT 5V; 24000 SYSTEM GATES ALSO AVAILABLE
maximum clock frequency320 MHz
Combined latency of CLB-Max0.7 ns
JESD-30 codeS-PQFP-G208
JESD-609 codee3
length28 mm
Humidity sensitivity level3
Configurable number of logic blocks1452
Equivalent number of gates16000
Number of entries175
Number of logical units1452
Output times175
Number of terminals208
Maximum operating temperature70 °C
Minimum operating temperature
organize1452 CLBS, 16000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)245
power supply3.3,3.3/5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width28 mm
Base Number Matches1
v3.2
SX Family FPGAs
u e
Leading Edge Performance
320 MHz Internal Performance
3.7 ns Clock-to-Out (Pin-to-Pin)
0.1 ns Input Setup
0.25 ns Clock Skew
Features
66 MHz PCI
CPLD and FPGA Integration
Single-Chip Solution
100% Resource Utilization with 100% Pin Locking
3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
Specifications
12,000 to 48,000 System Gates
Up to 249 User-Programmable I/O Pins
Up to 1,080 Flip-Flops
0.35 µ CMOS
SX Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
A54SX08
8,000
12,000
768
512
256
130
3
Yes
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
144
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
208
100
176
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
208
100
144, 176
A54SX32
32,000
48,000
2,880
1,800
1,080
249
3
Yes
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
208
144, 176
313, 329
June 2006
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
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