MC74VHC74DR2G datasheet, PDF - EEWORLD Datasheet

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MC74VHC74DR2G: DescriptionFlip Flops 2-5.5V CMOS Dual D-Type w/Set Reset; Categorylogic logic; File Size143KB，8 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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Flip Flops 2-5.5V CMOS Dual D-Type w/Set Reset

MC74VHC74DR2G Parametric

Parameter Name	Attribute value
Brand Name	ON Semiconductor
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	SOP, SOP14,.25
Contacts	14
Manufacturer packaging code	751A-03
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	1 week
series	AHC/VHC
JESD-30 code	R-PDSO-G14
JESD-609 code	e3
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	75000000 Hz
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of digits	1
Number of functions	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TR
Peak Reflow Temperature (Celsius)	260
power supply	2/5.5 V
Prop。Delay @ Nom-Sup	10.5 ns
propagation delay (tpd)	17.5 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
Trigger type	POSITIVE EDGE
width	3.9 mm
minfmax	110 MHz
Base Number Matches	1

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MC74VHC74

Dual D-Type Flip-Flop

with Set and Reset

The MC74VHC74 is an advanced high speed CMOS D−type

flip−flop fabricated with silicon gate CMOS technology. It achieves

high speed operation similar to equivalent Bipolar Schottky TTL

while maintaining CMOS low power dissipation.

The signal level applied to the D input is transferred to Q output

during the positive going transition of the Clock pulse.

Reset (RD) and Set (SD) are independent of the Clock (CP) and are

accomplished by setting the appropriate input Low.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

http://onsemi.com

MARKING

DIAGRAMS

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

SOEIAJ−14

M SUFFIX

CASE 965

VHC74

ALYWG

VHC

ALYWG

VHC74G

AWLYWW

•

High Speed: f

max

= 170MHz (Typ) at V

= 5V

Low Power Dissipation: I

= 2mA (Max) at T

= 25°C

High Noise Immunity: V

NIH

= V

NIL

= 28% V

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2.0 V to 5.5 V Operating Range

Low Noise: V

OLP

= 0.8 V (Max)

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300 mA

ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

•

Chip Complexity: 128 FETs or 32 Equivalent Gates

•

These Devices are Pb−Free and are RoHS Compliant

= Assembly Location

WL, L = Wafer Lot

Y, YY = Year

WW, W = Work Week

G or

= Pb−Free Package

(Note: Microdot may be in either location)

FUNCTION TABLE

RD1

CP1

SD1

RD2

CP2

SD2

Inputs

Outputs

No Change

Figure 1. LOGIC DIAGRAM

*Both outputs will remain high as long as Set and Re-

set are low, but the output states are unpredictable

if Set and Reset go high simultaneously.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Semiconductor Components Industries, LLC, 2011

May, 2011

−

Rev. 8

Publication Order Number:

MC74VHC74/D

MC74VHC74DR2G Related Products

	MC74VHC74DR2G	MC74VHC74DTR2G	NLV74VHC74DTR2G
Description	Flip Flops 2-5.5V CMOS Dual D-Type w/Set Reset	Flip Flops 2-5.5V CMOS Dual D-Type w/Set Reset	Trigger LOG CMOS D FLIP FLOP
series	AHC/VHC	AHC/VHC	MC74VHC74
Maximum operating temperature	85 °C	85 °C	+ 125 C
Minimum operating temperature	-40 °C	-40 °C	- 55 C
Brand Name	ON Semiconductor	ON Semiconductor	-
Is it lead-free?	Lead free	Lead free	-
Maker	ON Semiconductor	-	ON Semiconductor
Parts packaging code	SOIC	TSSOP	-
package instruction	SOP, SOP14,.25	TSSOP, TSSOP14,.25	-
Contacts	14	14	-
Manufacturer packaging code	751A-03	948G-01	-
Reach Compliance Code	compliant	compliant	-
Factory Lead Time	1 week	1 week	-
JESD-30 code	R-PDSO-G14	R-PDSO-G14	-
JESD-609 code	e3	e4	-
length	8.65 mm	5 mm	-
Load capacitance (CL)	50 pF	50 pF	-
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	-
Maximum Frequency@Nom-Sup	75000000 Hz	75000000 Hz	-
MaximumI(ol)	0.008 A	0.008 A	-
Humidity sensitivity level	1	1	-
Number of digits	1	1	-
Number of functions	2	2	-
Number of terminals	14	14	-
Output polarity	COMPLEMENTARY	COMPLEMENTARY	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	SOP	TSSOP	-
Encapsulate equivalent code	SOP14,.25	TSSOP14,.25	-
Package shape	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-
method of packing	TR	TR	-
Peak Reflow Temperature (Celsius)	260	260	-
power supply	2/5.5 V	2/5.5 V	-
Prop。Delay @ Nom-Sup	10.5 ns	10.5 ns	-
propagation delay (tpd)	17.5 ns	17.5 ns	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	1.75 mm	1.2 mm	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	-
Minimum supply voltage (Vsup)	2 V	2 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	-
surface mount	YES	YES	-
technology	CMOS	CMOS	-
Temperature level	INDUSTRIAL	INDUSTRIAL	-
Terminal surface	Tin (Sn)	Nickel/Palladium/Gold (Ni/Pd/Au)	-
Terminal form	GULL WING	GULL WING	-
Terminal pitch	1.27 mm	0.65 mm	-
Terminal location	DUAL	DUAL	-
Maximum time at peak reflow temperature	40	40	-
Trigger type	POSITIVE EDGE	POSITIVE EDGE	-
width	3.9 mm	4.4 mm	-
minfmax	110 MHz	110 MHz	-
Base Number Matches	1	1	-

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