128K x 36
IDT71V35761S/SA
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
◆
◆
Features
◆
◆
◆
128K x 36 memory configurations
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO
input selects interleaved or linear burst mode
3.3V core power supply
◆
◆
◆
◆
◆
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
Green parts available, see ordering information
Functional Block Diagram
LBO
ADV
CEN
Burst
Sequence
INTERNAL
ADDRESS
CLK
ADSC
ADSP
CLK EN
Binary
Counter
CLR
2
Burst
Logic
17/18
A0*
A1*
Q0
Q1
128K x 36-
BIT
MEMORY
ARRAY
2
A
0
,A
1
17/18
A
2
–A
17
36
36
A
0 -
A
16/17
GW
BWE
BW
1
ADDRESS
REGISTER
Byte 1
Write Register
Byte 1
Write Driver
9
Byte 2
Write Register
Byte 2
Write Driver
BW
2
Byte 3
Write Register
9
Byte 3
Write Driver
BW
3
Byte 4
Write Register
9
Byte 4
Write Driver
BW
4
9
OUTPUT
REGISTER
CE
CS
0
CS
1
D
Q
Enable
Register
CLK EN
DATA
INPUT
REGISTER
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
I/O
0
— I/O
31
I/O
P1
— I/O
P4
36
,
5301 drw 01
TMS
TDI
TCK
TRST
(Optional)
JTAG
(SA Version)
TDO
1
©2014 Integrated Device Technology, Inc.
NOVEMBER 2014
DSC-5301/07
11
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Description
The IDT71V35761 are high-speed SRAMs organized as
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating
the access sequence. The first cycle of output data will be pipelined
for one cycle before it is available on the next rising clock edge. If
burst mode operation is selected (ADV=LOW), the subsequent
three cycles of output data will be available to the user on the next
three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the
LBO
input pin.
The IDT71V35761 SRAMs utilize a high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array(fBGA).
Pin Description Summary
A
0
-A
17
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5301 tbl 01
6.42
2
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
-A
17
ADSC
ADSP
ADV
Pin Function
Address Inputs
Address Status
(Cache Controller)
Address Status
(Processor)
Burst Address
Advance
Byte Write Enable
I/O
I
I
I
I
Active
N/A
LOW
LOW
LOW
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and
ADSC
Low or
ADSP
Low and
CE
Low.
Synchronous Address Status from Cache Controller.
ADSC
is an active LOW input that is used to load the
address registers with new addresses.
Synchronous Address Status from Processor.
ADSP
is an active LOW input that is used to load the address
registers with new addresses.
ADSP
is gated by
CE.
Synchronous Address Advance.
ADV
is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs
BW
1
-BW
4
. If
BWE
is LOW at the rising edge of CLK
then
BWx
inputs are passed to the next stage in the circuit. If
BWE
is HIGH then the byte write inputs are
blocked and only
GW
can initiate a write cycle.
Synchronous byte write enables.
BW
1
controls I/O
0-7
, I/O
P1
,
BW
2
controls I/O
8-15
, I/O
P2
, etc. Any active byte
write causes all outputs to be disabled.
Synchronous chip enable.
CE
is used with CS
0
and
CS
1
to enable the IDT71V35761.
CE
also gates
ADSP.
This is the clock input. All timing references for the device are made with respect to this input.
Synchronous active HIGH chip select. CS
0
is used with
CE
and
CS
1
to enable the chip.
Synchronous active LOW chip select.
CS
1
is used with
CE
and CS
0
to enable the chip.
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK.
GW
supersedes individual byte write enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Asynchronous burst order selection input. When
LBO
is HIGH, the interleaved burst sequence is selected. When
LBO
is LOW the Linear burst sequence is selected.
LBO
is a static input and must not change state while the
device is operating.
Asynchronous output enable. When
OE
is LOW the data output drivers are enabled on the I/O pins if the chip is
also selected. When
OE
is HIGH the I/O pins are in a high-impedance state.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used
TRST
can
be left floating. This pin has an internal pullup. Only available in BGA package.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down.
3.3V core power supply.
3.3V I/O Supply.
Ground.
NC pins are not electrically connected to the device.
5301tbl 02
BWE
I
LOW
BW
1
-BW
4
CE
CLK
CS
0
CS
1
GW
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
Individual Byte
Write Enables
Chip Enable
Clock
Chip Select 0
Chip Select 1
Global Write
Enable
Data Input/Output
Linear Burst Order
I
I
I
I
I
I
I/O
I
LOW
LOW
N/A
HIGH
LOW
LOW
N/A
LOW
OE
TMS
TDI
TCK
TDO
Output Enable
Test ModeSelect
Test Data Input
Test Clock
Test DataOutput
JTAG Reset
(Optional)
Sleep Mode
Power Supply
Power Supply
Ground
No Connect
I
I
I
I
O
LOW
N/A
N/A
N/A
N/A
TRST
I
LOW
ZZ
V
DD
V
DDQ
V
SS
NC
I
N/A
N/A
N/A
N/A
HIGH
N/A
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3,6)
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Commercial
Operating Temperature
Industrial
Operating Temperature
Commercial &
Industrial
-0.5 to +4.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
-0 to +70
-40 to +85
-55 to +125
-55 to +125
2.0
50
Recommended Operating
Temperature and Supply Voltage
Unit
V
V
V
V
o
Grade
Commercial
Industrial
Temperature
(1)
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
V
DDQ
3.3V±5%
3.3V±5%
5301 tbl 04
V
TERM
(4,6)
V
TERM
(5,6)
NOTES:
1. T
A
is the "instant on" case temperature.
C
C
C
C
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
3.135
0
2.0
2.0
-0.3
(2)
Typ.
3.3
3.3
0
____
____
____
T
A
(7)
Max.
3.465
3.465
0
V
DD
+0.3
V
DDQ
+0.3
(1)
0.8
Unit
V
V
V
V
V
V
5301 tbl 06
o
T
BIAS
T
STG
P
T
I
OUT
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
o
V
SS
V
IH
V
IH
o
W
mA
5301 tbl 03
V
IL
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed V
DDQ
during power supply ramp up.
7. T
A
is the "instant on" case temperature.
NOTES:
1. V
IH
(max) = V
DDQ
+ 1.0V for pulse width less than t
CYC/2
, once per cycle.
2. V
IL
(min) = -1.0V for pulse width less than t
CYC/2
, once per cycle.
100 Pin TQFP Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
5301 tbl 07
119 BGA Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5301 tbl 07a
165 fBGA Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5301 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
/ NC
(1)
V
DD
NC
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(2)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
5301drw 02
,
NOTES:
1. Pin 14 can either be directly connected to V
DD
, or connected to an input voltage
≥
V
IH
, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
100 TQFP
Top View
6.42
5
Motor Drive Control（Motor Control）
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