STD7NS20
STD7NS20-1
N-CHANNEL 200V - 0.35Ω - 7A DPAK / IPAK
MESH OVERLAY™ MOSFET
PRELIMINARY DATA
TYPE
STD7NS20
STD7NS20-1
s
s
s
s
s
V
DSS
200 V
200 V
R
DS(on)
< 0.40
Ω
< 0.40
Ω
I
D
7A
7A
3
1
2
1
3
TYPICAL R
DS
(on) = 0.35
Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
DPAK
TO-252
IPAK
TO-251
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performance. The new patented STrip layout cou-
pled with the Company’s proprietary edge termina-
tion structure, makes it suitable in coverters for
lighting applications.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITH MODE POWER SUPPLIES (SMPS)
s
DC-DC CONVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
( )
P
TOT
dv/dt (1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 kΩ)
Gate- source Voltage
Drain Current (continuos) at T
C
= 25°C
Drain Current (continuos) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
Value
200
200
± 20
7
4.4
28
45
0.37
5
–65 to 150
150
(1) I
SD
≤
7A, di/dt≤300 A/µs, V
DD
≤
V
(BR)DSS
, Tj≤T
jMAX
Unit
V
V
V
A
A
A
W
W/°C
V/ns
°C
°C
(•)Pulse width limited by safe operating area
June 2003
1/8
STD7NS20 / STD7NS20-1
THERMAL DATA
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
2.7
100
275
°C/W
°C/W
°C
AVALANCHE CHARACTERISTICS
Symbol
I
AR
E
AS
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Max Value
7
60
Unit
A
mJ
ELECTRICAL CHARACTERISTICS
(TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
V
(BR)DSS
I
DSS
I
GSS
Parameter
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Test Conditions
I
D
= 250 µA, V
GS
= 0
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
V
GS
= ±20V
Min.
200
1
10
±100
Typ.
Max.
Unit
V
µA
µA
nA
ON (1)
Symbol
V
GS(th)
R
DS(on)
Parameter
Gate Threshold Voltage
Static Drain-source On
Resistance
Test Conditions
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 3.5 A
Min.
2
Typ.
3
0.35
Max.
4
0.40
Unit
V
Ω
DYNAMIC
Symbol
g
fs
(1)
C
iss
C
oss
C
rss
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 3.5 A
V
DS
= 25V, f = 1 MHz, V
GS
= 0
Min.
Typ.
4
540
90
35
Max.
Unit
S
pF
pF
pF
2/8
STD7NS20 / STD7NS20-1
ELECTRICAL CHARACTERISTICS
(CONTINUED)
SWITCHING ON
Symbol
t
d(on)
t
r
Q
g
Q
gs
Q
gd
Parameter
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V
DD
= 100 V, I
D
= 3.5 A
R
G
= 4.7Ω V
GS
= 10 V
(see test circuit, Figure 3)
V
DD
= 160V, I
D
= 18 A,
V
GS
= 10V
Min.
Typ.
10
15
31
7.5
9
45
Max.
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
Symbol
t
r(Voff)
t
f
t
c
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
V
clamp
= 160 V, I
D
= 7 A,
R
G
= 4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
Min.
Typ.
12
12
25
Max.
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
I
SD
I
SDM
(2)
V
SD
(1)
t
rr
Q
rr
I
RRM
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 7 A, V
GS
= 0
I
SD
= 7 A, di/dt = 100A/µs
V
DD
= 50V, T
j
= 150°C
(see test circuit, Figure 5)
170
0.95
11
Test Conditions
Min.
Typ.
Max.
7
28
1.5
Unit
A
A
V
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3/8
STD7NS20 / STD7NS20-1
Fig. 1:
Unclamped Inductive Load Test Circuit
Fig. 2:
Unclamped Inductive Waveform
Fig. 3:
Switching Times Test Circuit For
Resistive Load
Fig. 4:
Gate Charge test Circuit
Fig. 5:
Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/8
STD7NS20 / STD7NS20-1
TO-252 (DPAK) MECHANICAL DATA
mm
MIN.
A
A1
A2
B
B2
C
C2
D
E
G
H
L2
L4
V2
0.60
0
o
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
6.40
4.40
9.35
0.8
1.00
8
o
0.024
0
o
TYP.
MAX.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
6.60
4.60
10.10
MIN.
0.087
0.035
0.001
0.025
0.204
0.018
0.019
0.236
0.252
0.173
0.368
0.031
0.039
0
o
inch
TYP.
MAX.
0.094
0.043
0.009
0.035
0.213
0.024
0.024
0.244
0.260
0.181
0.398
DIM.
P032P_B
5/8
Analog electronics
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