FPGA - Field Programmable Gate Array FPGA - Stratix II 3022 LABs 492 IOs
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Intel |
| package instruction | BGA, BGA672,26X26,40 |
| Reach Compliance Code | compliant |
| ECCN code | 3A991 |
| maximum clock frequency | 717 MHz |
| Combined latency of CLB-Max | 4.45 ns |
| JESD-30 code | S-PBGA-B672 |
| JESD-609 code | e0 |
| length | 35 mm |
| Humidity sensitivity level | 3 |
| Configurable number of logic blocks | 24176 |
| Number of entries | 492 |
| Number of logical units | 60440 |
| Output times | 484 |
| Number of terminals | 672 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | |
| organize | 24176 CLBS |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | BGA |
| Encapsulate equivalent code | BGA672,26X26,40 |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | 220 |
| power supply | 1.2,1.5/3.3,3.3 V |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| Maximum seat height | 2.6 mm |
| Maximum supply voltage | 1.25 V |
| Minimum supply voltage | 1.15 V |
| Nominal supply voltage | 1.2 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | OTHER |
| Terminal surface | TIN LEAD |
| Terminal form | BALL |
| Terminal pitch | 1.27 mm |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | 30 |
| width | 35 mm |
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