19-2391; Rev 2; 2/07
+3.3V, 10.7Gbps Limiting Amplifier
General Description
The MAX3971A is a compact 10.7Gbps limiting amplifier.
It accepts signals over a wide range of input voltage levels
and provides constant-level output voltages with con-
trolled edge speeds. It functions as a data quantizer with
a 240mV
P-P
differential CML output signal with a 100Ω dif-
ferential termination. The MAX3971A has a disable func-
tion that allows the outputs to be squelched if required by
the application.
The MAX3971A is designed to work with the MAX3970
transimpedance amplifier (TIA). The limiting amplifier
operates on a single +3.3V supply and functions over a
0°C to +85°C temperature range.
The MAX3971A is offered in die form and in a compact
4mm
×
4mm 20-pin QFN and thin QFN package.
♦
Single +3.3V Power Supply
♦
2mV
P-P
Input Sensitivity
♦
1.8ps Typical Deterministic Jitter (V
IN
= 800mV
P-P
)
♦
Dice and 4mm
×
4mm QFN or Thin QFN Package
Available
♦
Output Disable Feature
Features
MAX3971A
Ordering Information
Applications
VSR OC-192 Receivers
10Gbps Ethernet Optical Receivers
10Gbps Fibre Channel Receivers
MAX3971AUGP
MAX3971AUTP
MAX3971AUTP+
MAX3971AU/D
0°C to +85°C 20 QFN-EP*
PART
TEMP RANGE PIN-PACKAGE
PKG
CODE
G2044-4
0°C to +85°C 20 Thin QFN-EP* T2044-3
0°C to +85°C 20 Thin QFN-EP* T2044-3
0°C to +85°C Dice**
—
Pin Configurations appear at end of data sheet.
*EP
= Exposed pad.
**Dice
are designed to operate over a 0°C to +110°C junction-
temperature (T
J
) range, but are tested and guaranteed at
T
A
= +25°C.
+Denotes
lead-free package.
Typical Application Circuit
+3.3V
0.1μF
+3.3V
CZ-
GNDIN+
0.1μF
IN+
100Ω
IN-
GNDIN-
OUT-
50Ω
OUT+
0.1μF
50Ω
CZ+
SUPPLY FILTER
V
CC1
V
CC2
V
CC3
TIA
0.1μF
0.1μF
MAX3970
MAX3971A
DISABLE
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 10.7Gbps Limiting Amplifier
MAX3971A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC1
, V
CC2
, V
CC3
......................-0.5V to +5.0 V
Voltage at IN+, IN-, DISABLE, CZ+, CZ-,
OUT+, OUT- .........................................+0.5V to (V
CC
+ 0.5V)
Differential Voltage Between CZ+ and CZ- ...........................±1V
Differential Voltage Between IN+ and IN-...........................±2.5V
Continuous Power Dissipation (T
A
= +85°C)
20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W
Operating Ambient Temperature Range .............-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, output load = 50Ω to V
CC
, T
A
= 0°C to +85°C, unless otherwise noted. All AC parameters are measured with
a 2
23
- 1 PRBS pattern applied to the input at 10.7Gbps. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Supply Current
Small-Signal Bandwidth
Input Sensitivity
Input Overload
Low-Frequency Cutoff
SYMBOL
I
CC
BW
V
IN-min
V
IN-max
(Notes 1, 2)
(Note 1)
CZ = 0.1µF (Note 1)
5mV
P-P
input (Notes 1, 3)
Deterministic Jitter
10mV
P-P
input (Notes 1, 3)
800mV
P-P
input (Notes 1, 3)
1200mV
P-P
input (Notes 1, 3)
Random Jitter
Transition Time
Data Input Impedance
Data Output-Voltage Swing
Data Output Voltage when
Disabled
Data Output Common-Mode
Voltage
Data Output Impedance
Data Output Offset when
DISABLE is High
Disable Input Current
DISABLE High Voltage
DISABLE Low Voltage
Disable Response Time
V
IH
V
IL
20
2
0.8
Single ended
42
t
r
, t
f
20mV
P-P
< input < 1200mV
P-P
(Notes 1, 4)
20% to 80%, differential output (Note 1)
Single ended
Differential signal amplitude between
OUT+ and OUT-
Differential signal amplitude
between OUT+ and OUT-
42
190
1200
60
5.2
3.5
1.8
1.9
0.6
20
50
240
0.25
V
CC
-
75
50
75
30
58
200
60
75
16.0
14.0
7.0
11.0
1.1
30
58
400
50
ps
RMS
ps
Ω
mV
P-P
mV
P-P
mV
Ω
mV
µA
V
V
ns
ps
CONDITIONS
MIN
TYP
50
10
2
5
MAX
85
UNITS
mA
GHz
mV
P-P
mV
P-P
kHz
Note 1:
Guaranteed by design and characterization.
Note 2:
The output signal amplitude at the sensitivity is > .95
✕
the amplitude with large input.
Note 3:
Deterministic jitter is measured with K28.5 pattern (0011 1110 1011 0000 0101) at 10.7Gbps. It is the peak-to-peak devia-
tion from the ideal time crossing, measured at the zero-level crossing of the differential output.
Note 4:
For a bit-error rate of 10
-12
, the peak-to-peak random jitter is 14.1
✕
the RMS random jitter.
2
_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
Typical Operating Characteristics
(V
CC
= +3.3V, output load = 50Ω to V
CC
, T
A
= +25°C, unless otherwise noted.)
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 10mV
P-P
, AT 10.7Gbps)
MAX3971A toc01
MAX3971A
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 5mV
P-P
, AT 10.3Gbps)
MAX3971A toc02
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 1200mV
P-P
, AT 10.3Gbps)
2
23
- 1PRBS
MAX3971A toc03
MAX39971A toc09
MAX3971A toc06
2
23
- 1PRBS
2
23
- 1PRBS
45mV/div
45mV/div
45mV/div
20ps/div
20ps/div
20ps/div
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 800mV
P-P
, AT 10.7Gbps)
MAX3971A toc04
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
58
56
SUPPLY CURRENT (mA)
54
GAIN (dB)
52
50
48
46
44
42
40
MAX3971A toc05
SMALL-SIGNAL GAIN
50
45
40
35
30
25
20
15
10
5
0
MAX3971A UGP
60
2
23
- 1PRBS
45mV/div
20ps/div
0
10
20
30
40
50
60
70
80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FREQUENCY (GHz)
TEMPERATURE (°C)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX3971A toc07
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3971A toc08
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
6
5
4
3
2
10.7Gbps, K28.5,
V
CC
= +3V, TEMP = 85°C
270
250
230
210
190
170
150
0
1
2
3
V
IN
(mV
P-P
)
4
5
6
3.5
3.0
RANDOM JITTER (ps
RMS
)
2.5
2.0
1.5
1.0
0.5
0
1
10
100
1000
JITTER (ps
P-P
)
V
OUT
(mV
P-P
)
1
0
10,000
1
10
100
1000
10,000
INPUT AMPLITUDE (mV
P-P
)
INPUT AMPLITUDE (mV
P-P
)
_______________________________________________________________________________________
3
+3.3V, 10.7Gbps Limiting Amplifier
MAX3971A
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, output load = 50Ω to V
CC
, T
A
= +25°C, unless otherwise noted.)
DETERMINISTIC JITTER
vs. TEMPERATURE
10.7Gbps with K28.5
6
5
JITTER (ps
P-P
)
LOSS (dB)
4
3
2
1
0
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE (°C)
V
IN
= 800mV
V
IN
= 5mV
MAX3971A toc10
INPUT RETURN LOSS (S11)
(V
CC
= +3.3V)
MAX3971A toc11
OUTPUT RETURN LOSS (S22)
(V
CC
= +3.3V)
-5
-10
-15
LOSS (dB)
MAX3971A
MAX3971A toc12
7
0
-5
-10
-15
-20
-25
MAX3971A
0
-20
-25
-30
-35
-40
-30
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
-45
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
OUTPUT NOISE POWER
(INPUT CONNECTED TO 50Ω TO GND)
MAX3971A toc13
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX3971A toc14
INPUT COMMON-MODE REJECTION
RATIO vs. FREQUENCY
V
IN
= V
IN+
= V
IN-
MAX3971A toc15
-19.0
-19.1
NOISE POWER (dBm)
-19.2
45
70
65
60
CMRR (dB)
55
50
45
40
PSRR (dB)
35
-19.3
-19.4
-19.5
-19.6
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
30
PSRR = -20log
ΔV
OUT
/ΔV
CC
10k
100k
1M
FREQUENCY (Hz)
10M
100M
40
CMRR = -20log(V
OUT
/V
IN
)
100
1M
10M
100M
1G
10G
FREQUENCY (Hz)
4
_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
Pin Description
PIN
1
2
3
4
5, 7, 9, 10
6, 8, 11
12, 15
13
14
16
17
18
19
20
—
NAME
GNDIN+
IN+
IN-
GNDIN-
N.C.
GND
V
CC3
OUT-
OUT+
DISABLE
V
CC2
CZ+
CZ-
V
CC1
EP
Noninverting Input Signal
Inverting Input Signal
Input Ground for Shielding Input Signal IN-. Not connected internally.
No Connection. Leave unconnected.
Ground
Output Circuitry Power Supply
Inverting Output of Amplifier
Noninverting Output of Amplifier
When DISABLE is connected to V
CC
or left floating, outputs are disabled. When DISABLE is
connected to GND, outputs are enabled.
Power Supply to Circuitry other than Input and Output Circuits
Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the
Detailed
Description
section.
Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the
Detailed
Description
section.
Input Circuitry Power Supply
Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation.
FUNCTION
Input Ground for Shielding Input Signal IN+. Not connected internally.
MAX3971A
Detailed Description and
Applications Information
Figure 1 is a functional diagram of the MAX3971A limit-
ing amplifier. The signal path consists of an input buffer
followed by a gain stage and output amplifier. A feed-
back loop provides offset correction by driving the
average value of the differential output to zero.
CZ
Gain Stage and Offset Correction
The limiting amplifier provides approximately 42dB
gain. The large gain makes the amplifier susceptible to
small DC offsets, which cause deterministic jitter. A
low-frequency loop is integrated into the limiting ampli-
fier to reduce output offset, typically to less than 2mV.
The external capacitor (CZ) is required for stability and
to set the low-frequency cutoff for the offset correction
loop. The time constant of the loop is set by the product
of an equivalent 20kΩ on-chip resistor and the value of
the off-chip capacitor (CZ). For stable operation, the
minimum value of CZ is 0.01µF. To minimize pattern-
dependent jitter, CZ should be as large as possible.
For 10Gbps ethernet and SONET applications, the typi-
cal value of CZ is 0.1µF. Keep CZ close to the package
to reduce parasitic inductance.
CZ-
CZ+
DISABLE
MAX3971A
GNDIN+
IN+
100Ω
IN-
INPUT
AMPLIFIER
OFFSET
CORRECTION
AMP
LOWPASS
FILTER
OUT+
CML Input Circuit
GAIN
42dB
OUTPUT
AMPLIFIER
OUT-
GNDIN-
The input buffer is designed to accept CML input sig-
nals such as the output from the MAX3970 transimped-
ance amplifier. An equivalent circuit for the input is
shown in Figure 2. For lowest deterministic jitter in all
operating conditions, AC-coupling capacitors are rec-
ommended on the input.
Figure 1. Functional Diagram
_______________________________________________________________________________________
5
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