K9F1G08Q0A
K9F1G08U0A
FLASH MEMORY
Document Title
128M x 8 Bit
NAND Flash Memory
Revision History
Revision No
0.0
0.1
History
1. Initial issue
1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 23~26)
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added Addressing method for program operation
Draft Date
Aug. 24. 2003
Jan. 27. 2004
Remark
Advance
Preliminary
0.2
0.3
1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
1. PKG(TSOP1, WSOP1) Dimension Change
Apr. 23. 2004
May. 19. 2004
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9F1G08Q0A
K9F1G08U0A
FLASH MEMORY
128M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F1G08Q0A
K9F1G08U0A-Y,P
K9F1G08U0A-V,F
Vcc Range
1.70 ~ 1.95V
2.7 ~ 3.6V
X8
Organization
PKG Type
Only available in MCP
TSOP1
WSOP1
FEATURES
•
Voltage Supply
-1.8V device(K9F1G08Q0A): 1.70V~1.95V
-3.3V device(K9F1G08U0A): 2.7 V ~3.6 V
•
Organization
- Memory Cell Array : (128M + 4,096K)bit x 8bit
- Data Register : (2K + 64)bit x8bit
- Cache Register : (2K + 64)bit x8bit
•
Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
•
Page Read Operation
- Page Size : 2K-Byte
- Random Read : 25µs(Max.)
- Serial Access : 30ns(Min.) : (K9F1G08U0A)
50ns(Min.) : (K9F1G08Q0A)
•
Fast Write Cycle Time
- Program time : 300µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Cache Program Operation for High Performance Program
•
Intelligent Copy-Back Operation
•
Unique ID for Copyright Protection
•
Package :
- K9F1G08U0A-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1G08U0A-VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F1G08U0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F1G08U0A-FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1G08U0A-V,F(WSOPI ) is the same device as
K9F1G08U0A-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 50ns (30ns, K9F1G08U0A)
cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write
controller automates all program and erase functions including pulse repetition, where required, and internal verification and margin-
ing of data. Even the write-intensive systems can take advantage of the K9F1G08X0A′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08X0A is an optimum solution for
large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
2
K9F1G08Q0A
K9F1G08U0A
PIN CONFIGURATION (TSOP1)
K9F1G08X0A-YCB0,PCB0/YIB0,PIB0
X8
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FLASH MEMORY
X8
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
18.40
±0.10
0.724
±0.004
+0.075
20.00
±0.20
0.787
±0.008
0.20
-0.03
+0.07
#1
0.008
-0.001
0.16
-0.03
+0.07
+0.003
0.50
0.0197
12.00
0.472
0.05
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
3
0.005
-0.001
+0.003
1.20
0.047MAX
K9F1G08Q0A
K9F1G08U0A
PIN CONFIGURATION (WSOP1)
K9F1G08U0A-VIB0,FIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
15.40
±0.10
0.58
±0.04
#1
+0.07
-0.03
#48
+0.07
-0.03
0.16
12.40MAX
12.00
±0.10
0.50TYP
(0.50
±
0.06)
0.20
#24
#25
(0.01Min)
0.10
+0.075
-0.035
8
°
0
°
~
0.45~0.75
17.00
±0.20
4
K9F1G08Q0A
K9F1G08U0A
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
Pin Function
FLASH MEMORY
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
N.C
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
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