G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Features :
∗
∗
∗
∗
∗
∗
∗
∗
∗
4,194,304 words by 4 bits organization.
Fast access time and cycle time
Low power dissipation.
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden Refresh.
Description :
The GLT4160L04 is a high-performance
CMOS dynamic random access memory
containing 16,777,216 bits organized in a x4
configuration. The GLT4160L04 offers page
cycle access with Extended Data Output.
The GLT4160L04 has 11 row- and 11
column-addresses, and accepts 2048-cycle
refresh in 32 ms.
The GLT4160L04 provides EDO PAGE
MODE operation which allows for fast data
access within a row-address defined
boundary, up to 2048 x 4 bits with cycle
times as short as 18ns.
2,048 refresh cycles per 32ms.
Available in 300 mil 26(24) SOJ and TSOPII.
3.3V±0.3V Vcc Power Supply voltage
.
All inputs and Outputs are LVTTL compatible.
Extended Data-Out (EDO) Page access
cycle.
∗
Self-refresh Capability
. (S-Version).
HIGH PERFORMANCE
Max.
RAS
Access Time, (t
RAC
)
Max. Column Address Access Time, (t
AA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
Max.
CAS
Access Time (t
CAC
)
40
40 ns
20 ns
18 ns
70 ns
12 ns
50
50 ns
25 ns
20 ns
84 ns
13 ns
60
60 ns
30 ns
25 ns
70
70 ns
35 ns
30 ns
104 ns 124 ns
15 ns
20 ns
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
-1-
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Pin Configuration :
GLT4160L04
300mil 26(24) SOJ
V
cc
DQ
0
DQ
1
WE
RAS
NC
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ
3
DQ
2
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
cc
DQ
0
DQ
1
WE
RAS
NC
A
10
A
0
A
1
A
2
A
3
V
CC
GLT4160L04
300mil 26(24) TSOPII
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ
3
DQ
2
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Descriptions:
Name
A
0
- A
10
RAS
CAS
WE
OE
Function
Address Inputs
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Data Inputs / Outputs
+3.3V Power Supply
Ground
No Connection
DQ
0
- DQ
3
V
CC
V
SS
NC
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
-2-
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Absolute Maximum Ratings*
Capacitance*
T
A
=25°C, V
CC
=3.3V±0.3V, V
SS
=0V
Max. Unit
5
7
7
pF
pF
pF
Operating Temperature, T
A
(ambient)
Symbol
Parameter
.............................................….0°C to
+70°C
C
IN1
Address Input
For Extended Temperature……………..-20°C to 85°C
C
IN2
RAS, CAS, WE, OE
Storage Temperature(plastic)............-55°C to +150°C
Voltage Relative to V
SS
........................-0.5V to + 4.6V
C
OUT
Data Input/Output
Short Circuit Output Current...............................20mA
Power Dissipation...............................................1.0W
*Note: Operation above Absolute Maximum Ratings can
aversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
l
All voltages are referenced to GND.
After power up, wait more than 200µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
WE
CAS
DATA-IN
BUFFER
4
DQ
0
DQ
1
DQ
2
DQ
3
NO.2 CLOCK
GENERATOR
DATA-OUT
BUFFER
4
4
OE
COLUMN-
ADDRESS
BUFFER(11)
11
COLUMN
DECODER
2048
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
4
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
11
REFRESH
COUNTER
2048
11
ROW
ADDRESS
BUFFERS(11)
ROW DECODER
11
2048
2048 x 1024 x 4
MEMORY
ARRAY
RAS
NO.1 CLOCK
GENERATOR
V
DD
V
SS
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
-3-
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Truth Table:
Function
Standby
READ
EARLY WRITE
READ WRITE
EDO-PAGE-MODE
READ
EDO-PAGE-MODE
EARLY-WRITE
EDO-PAGE-MODE
READ-WRITE
RAS
-ONLY REFRESH
RAS
H
L
L
L
1st Cycle
2nd cycle
1st Cycle
2nd cycle
1st Cycle
2nd cycle
L
L
L
L
L
L
L
READ
L→H→L
H→L
H→L
CAS
H→X
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
L
L
WE
X
H
L
H→L
H
H
L
L
H→L
H→L
X
H
L
H
H
OE
X
L
X
L→H
L
L
X
X
L→H
L→H
X
L
X
X
X
ADDRESS
t
R
t
C
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
X
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
X
X
DATA-IN/OUT
DQ1-DQ4
High-Z
Data-Out
Data-In
Data-Out,Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out,Data-In
Data-Out,Data-In
High-Z
Data-Out
Data-In
High-Z
High-Z
HIDDEN REFRESH
CBR REFRESH
SELF REFRESH
WRITE L→H→L
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
-4-
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
DC and Operating Characteristics (1-2)
T
A
= 0°C to 70°C, -20°C to 85°C V
CC
=3.3V±0.3V, V
SS
=0V, unless otherwise specified.
Sym.
I
LI
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
Operating Current,
Random READ/WRITE
Test Conditions
0V
≤
V
IN
≤
V
CC
+0.3V
(All other pins not under
test=0V)
0V
≤
V
out
≤
V
CC
Output is disabled (Hiz)
t
RC
= t
RC
(min.)
Access
Time
Min.
-5
Typ
Max.
+5
Unit Notes
µA
I
LO
I
CC1
-5
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
+5
130
120
80
70
1
µA
1,2
mA
I
CC2
Standby Current (TTL)
RAS
,
CAS
at V
IH
other inputs
≥V
SS
mA
2
mA
I
CC3
Refresh Current,
RAS
cycling,
CAS
at V
IH
t
RC
= t
RC
(min.)
RAS
-Only
I
CC4
Operating Current,
EDO Page Mode
RAS
at V
IL
,
CAS
address
cycling:t
PC
=t
PC
(min.)
I
CC5
Refresh Current,
RAS
,
CAS
address cycling:
t
RC
=t
RC
(min.)
CAS
Before
RAS
I
CC6
Standby Current, (CMOS)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
130
120
80
70
130
120
80
70
130
120
80
70
1,2
mA
mA
1
RAS
≥V
CC
-0.2V,
CAS
≥V
CC
-0.2V,
All other inputs V
SS
300
µA
1,5
I
CC7
Self refresh Current
RAS
=
CAS
=0.2V,
WE = OE = A
0
~A
10
=V
CC
-0.2V or
0.2V
DQ
0
~DQ
3
=V
CC
-0.2V,0.2V or
Open
300
µA
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.3
2.0
I
OL
= 2mA
I
OH
= -2mA
2.4
+0.8
V
CC
+0.3
0.4
V
V
V
V
3
4
Notes:
1. I
CC
is dependent on output loading when the device output is selected. Specified I
CC
(max.) is measured with the output open.
2. I
CC
is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle
in random Read/Write and EDO Fast Page Mode.
3. Specified V
IL
(min.) is steady state operation. During transitions V
IL
(min.) may undershoot to –1V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)≥V
SS
and V
IH
(max.)≤V
CC
.
4. Specified V
IH
(max.) is steady state operation . During transitions V
IH
(max.) may overshoot to V
CC
+1V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)
≥
V
SS
and VIH(max.)
≤
V
CC
.
5. S-Version.
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
-5-
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