EEWORLDEEWORLDEEWORLD

Part Number

Search

5SGXMA7N1F45C2LN

Description
FPGA - Field Programmable Gate Array FPGA - Stratix V GX 2560 LABS 840 IOs
CategoryProgrammable logic devices    Programmable logic   
File Size812KB,23 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Environmental Compliance
Download Datasheet Parametric View All

5SGXMA7N1F45C2LN Online Shopping

Suppliers Part Number Price MOQ In stock  
5SGXMA7N1F45C2LN - - View Buy Now

5SGXMA7N1F45C2LN Overview

FPGA - Field Programmable Gate Array FPGA - Stratix V GX 2560 LABS 840 IOs

5SGXMA7N1F45C2LN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIntel
package instructionFBGA-1932
Reach Compliance Codecompliant
JESD-30 codeS-PBGA-B1932
length45 mm
Configurable number of logic blocks23472
Number of entries840
Number of logical units622000
Output times840
Number of terminals1932
Maximum operating temperature85 °C
Minimum operating temperature
organize23472 CLBS
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1932,44X44,40
Package shapeSQUARE
Package formGRID ARRAY
power supply0.85,1.5,2.5,2.5/3,1.2/3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.9 mm
Maximum supply voltage0.88 V
Minimum supply voltage0.82 V
Nominal supply voltage0.85 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width45 mm
2015.10.01
Stratix V Device Overview
Subscribe
Send Feedback
SV51001
Altera’s 28-nm Stratix
®
V FPGAs include innovations such as an enhanced core architecture, integrated
transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual
property (IP) blocks.
With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices optimized for:
• Bandwidth-centric applications and protocols, including PCI Express
®
(PCIe
®
) Gen3
• Data-intensive applications for 40G/100G and beyond
• High-performance, high-precision digital signal processing (DSP) applications
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of
applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-
risk, low-cost path to HardCopy
®
V ASICs.
Related Information
Stratix V Device Handbook: Known Issues
Lists the planned updates to the
Stratix V Device Handbook
chapters.
Stratix V Family Variants
The Stratix V device family contains the GT, GX, GS, and E variants.
Stratix V GT
devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications
that require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communica‐
tions systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and
GX channels, respectively.
Stratix V GX
devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These
transceivers also support backplane and optical interface applications. These devices are optimized for
high-performance, high-bandwidth applications such as 40G/100G optical transport, packet processing,
and traffic management found in wireline, military communications, and network test equipment
markets.
Stratix V GS
devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18
or 1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps
data rate capability. These transceivers also support backplane and optical interface applications. These
devices are optimized for transceiver-based DSP-centric applications found in wireline, military,
broadcast, and high-performance computing markets.
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
©
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号