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HY5PS1G821LM-E3

Description
1Gb DDR2 SDRAM(DDP)
Categorystorage    storage   
File Size1MB,79 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HY5PS1G821LM-E3 Overview

1Gb DDR2 SDRAM(DDP)

HY5PS1G821LM-E3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSK Hynix
Parts packaging codeBGA
package instructionLFBGA, BGA63,9X11,32
Contacts63
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B63
JESD-609 codee0
length14 mm
memory density1073741824 bit
Memory IC TypeDDR DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals63
word count134217728 words
character code128000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize128MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Encapsulate equivalent codeBGA63,9X11,32
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.35 mm
self refreshYES
Continuous burst length4,8
Maximum standby current0.012 A
Maximum slew rate0.275 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width12.33 mm
HY5PS1G421(L)M
HY5PS1G821(L)M
1Gb DDR2 SDRAM(DDP)
HY5PS1G421(L)M
HY5PS1G821(L)M
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Oct. 2005
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