IC62C1024AL
Document Title
128K x 8 Low Power CMOS SRAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
May 7,2002
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002
1
IC62C1024AL
128K x 8 LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 35, 45, 55, 70 ns
•
Low active power: 450 mW (typical)
•
Low standby power: 150 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
DESCRIPTION
The
ICSI
IC62C1024AL is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using
ICSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62C1024L is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 x 2048
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002
IC62C1024AL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to + 7.0
–45 to + 85
–65 to + 150
1.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.4
—
2.2
–0.3
–2
–10
–2
–10
Max.
—
0.4
V
CC
+ 0.5
0.8
2
10
2
10
Unit
V
V
V
V
µA
µA
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
Com.
Ind.
Com.
Ind.
Notes:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
1
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
Com.
Ind.
-35 ns
Min. Max.
—
—
—
—
—
—
100
110
10
15
500
750
-45 ns
Min. Max.
—
—
—
—
—
—
90
100
10
15
500
750
-55 ns
Min. Max.
—
—
—
—
—
—
80
90
10
15
500
750
-70 ns
Min. Max.
—
—
—
—
—
—
70
80
10
15
500
750
Unit
mA
mA
V
CC
= Max.,
Com.
V
IN
= V
IH
or V
IL
,
CE1
≥
V
IH
, Ind.
or CE2
≤
V
IL
, f = 0
V
CC
= Max.,
Com.
CE1
≤
V
CC
– 0.2V,
Ind.
CE2
≤
0.2V, V
IN
> V
CC
– 0.2V,
or V
IN
≤
0.2V, f = 0
I
SB
2
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
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Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002
IC62C1024AL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE1
Access Time
CE2 Access Time
OE
Access Time
-35
Min. Max.
35
—
3
—
—
—
0
0
3
3
0
—
35
—
35
35
10
—
10
—
—
10
-45
Min. Max.
45
—
3
—
—
—
0
0
5
5
0
—
45
—
45
45
20
—
15
—
—
15
-55
Min. Max.
55
—
3
—
—
—
0
0
7
7
0
—
55
—
55
55
25
—
20
—
—
20
-70
Min. Max.
70
—
3
—
—
—
0
0
10
10
0
—
70
—
70
70
35
—
25
—
—
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
1
t
ACE
2
t
DOE
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
1
(2)
CE1
to Low-Z Output
t
LZCE
2
(2)
CE2 to Low-Z Output
t
HZCE
(2)
CE1
or CE2 to High-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
480
Ω
5V
5V
480
Ω
OUTPUT
100 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1a.
Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002
Figure 1b.
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