Data Sheet
FEATURES
14-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter (ADC)
AD9642
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+
VIN–
VCM
SCLK
SDIO
CSB
CLK+
CLK–
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
Figure 1.
GENERAL DESCRIPTION
The
AD9642
is a 14-bit analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The
AD9642
is designed to
support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converter to maintain excellent performance.
The ADC output data is routed directly to the external
14-bit LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a
3-wire SPI-compatible serial interface.
The
AD9642
is available in a 32-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
3-pin, 1.8 V SPI port for register programming and readback.
Pin compatibility with the
AD9634,
allowing a simple migra-
tion from 14 bits to 12 bits, and with the
AD6672.
Rev. B
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09995-001
SNR = 71.0 dBFS at 185 MHz A
IN
and 250 MSPS
SFDR = 83 dBc at 185 MHz A
IN
and 250 MSPS
−152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A
IN
, 250 MSPS
Total power consumption: 390 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy saving power-down modes
PIPELINE
14-BIT
ADC
14
D0±/D1±
AD9642
PARALLEL
DDR LVDS
AND
DRIVERS
D12±/D13±
DCO±
REFERENCE
SERIAL PORT
1-TO-8
CLOCK
DIVIDER
AD9642
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADC DC Specifications ............................................................... 3
ADC AC Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Equivalent Circuits ......................................................................... 16
Data Sheet
Theory of Operation ...................................................................... 17
ADC Architecture ...................................................................... 17
Analog Input Considerations ................................................... 17
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 19
Power Dissipation and Standby Mode .................................... 20
Digital Outputs ........................................................................... 20
Serial Port Interface (SPI) .............................................................. 22
Configuration Using the SPI ..................................................... 22
Hardware Interface ..................................................................... 22
SPI Accessible Features .............................................................. 23
Memory Map .................................................................................. 24
Reading the Memory Map Register Table............................... 24
Memory Map Register Table ..................................................... 25
Applications Information .............................................................. 27
Design Guidelines ...................................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
1/15—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Reading the Memory Map Register Table
Section .............................................................................................. 24
Changes to Table 13 ........................................................................ 26
7/14—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Full Power Bandwidth Parameter, Table 2 ................ 5
Deleted Noise Bandwidth Parameter, Table 2............................... 5
7/11—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AD9642
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance
2
Input Resistance
3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
I
AVDD1
I
DRVDD1
POWER CONSUMPTION
Sine Wave Input (DRVDD = 1.8 V)
Standby Power
4
Power-Down Power
1
2
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
25°C
AD9642-170
Min
Typ
Max
14
Guaranteed
±11
+2/−11
±0.5
±0.3
±1.3
±0.6
±7
±52
0.83
AD9642-210
Min
Typ
Max
14
Guaranteed
±11
+3.5/−8
±0.55
±0.3
±2.0
±0.75
±7
±105
0.85
AD9642-250
Min
Typ
Max
14
Guaranteed
±10
+3/−7
±0.6
±0.32
±2.5
±1.0
±7
±75
0.85
Unit
Bits
1
mV
%FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
rms
V p-p
pF
kΩ
V
Full
Full
Full
Full
1.75
2.5
20
0.9
1.75
2.5
20
0.9
1.75
2.5
20
0.9
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.8
123
50
311
50
5
1.9
1.9
136
64
360
1.7
1.7
1.8
1.8
129
56
333
50
5
1.9
1.9
139
67
371
1.7
1.7
1.8
1.8
136
64
360
50
5
1.9
1.9
146
69
387
V
V
mA
mA
mW
mW
mW
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).
Rev. B | Page 3 of 28
AD9642
ADC AC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless
otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 30 MHz
f
IN
= 90 MHz
1
Temperature
25°C
25°C
Full
25°C
25°C
Full
25°C
AD9642-170
Min
Typ
Max
72.5
72.2
70.7
71.8
71.2
70.7
AD9642-210
Min
Typ
Max
72.4
72.2
70.0
71.6
71.5
AD9642-250
Min
Typ
Max
72.2
72.0
71.8
71.4
68.6
70.9
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
f
IN
= 140 MHz
f
IN
= 185 MHz
f
IN
= 220 MHz
SIGNAL-TO-NOISE AND DISTORTION
(SINAD)
f
IN
= 30 MHz
f
IN
= 90 MHz
f
IN
= 140 MHz
f
IN
= 185 MHz
f
IN
= 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 30 MHz
f
IN
= 90 MHz
f
IN
= 140 MHz
f
IN
= 185 MHz
f
IN
= 220 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
= 30 MHz
f
IN
= 90 MHz
f
IN
= 140 MHz
f
IN
= 185 MHz
f
IN
= 220 MHz
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
f
IN
= 30 MHz
f
IN
= 90 MHz
f
IN
= 140 MHz
f
IN
= 185 MHz
f
IN
= 220 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 30 MHz
f
IN
= 90 MHz
f
IN
= 140 MHz
f
IN
= 185 MHz
f
IN
= 220 MHz
71.0
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
71.5
71.3
69.6
70.8
70.3
69.7
11.6
11.6
11.5
11.4
11.3
−96
−95
−82
−97
−86
−84
68.7
71.5
71.3
70.6
70.5
67.5
70.1
11.6
11.6
11.4
11.4
11.3
−96
−92
−79
−94
−95
−84
71.2
71.0
70.9
70.4
70.0
11.5
11.5
11.5
11.4
11.3
−90
−89
−90
−86
−80
−86
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
96
95
82
97
86
84
−99
−95
−87
−98
−96
−97
79
96
92
94
95
80
84
−98
−97
−81
−96
−97
−94
90
89
90
86
86
−95
−98
−97
−96
−81
−95
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. B | Page 4 of 28
Data Sheet
Parameter
TWO-TONE SFDR
f
IN
= 184.1 MHz, 187.1 MHz (−7 dBFS)
FULL POWER BANDWIDTH
1
1
AD9642
Temperature
25°C
25°C
AD9642-170
Min
Typ
Max
87
1000
AD9642-210
Min
Typ
Max
88
1000
AD9642-250
Min
Typ
Max
88
1000
Unit
dBc
MHz
See the
AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation,
for a complete set of definitions.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)
1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)
2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)
1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
LVDS Data and OR Outputs (OR+, OR−)
Differential Output Voltage (V
OD
), ANSI Mode
Output Offset Voltage (V
OS
), ANSI Mode
Differential Output Voltage (V
OD
), Reduced Swing Mode
Output Offset Voltage (V
OS
), Reduced Swing Mode
1
2
Temperature
Min
Typ
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
0.3
AGND
0.9
10
−22
12
1.22
0
50
−5
CMOS/LVDS/LVPECL
0.9
3.6
AVDD
1.4
22
−10
4
15
18
2.1
0.6
71
+5
26
2
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
1.22
0
45
−5
26
2
1.22
0
45
−5
26
5
2.1
0.6
70
+5
2.1
0.6
70
+5
Full
Full
Full
Full
250
1.15
150
1.15
350
1.25
200
1.25
450
1.35
280
1.35
mV
V
mV
V
Pull-up.
Pull-down.
Rev. B | Page 5 of 28
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