Si5348 Rev D Data Sheet
Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary
(T-BC) and Slave (T-SC) Clocks
The Si5348 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLs
™
are individually configurable as a SyncE PLL, IEEE
1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digital-
ly controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588
(PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/
OCXO reference input to determine the device’s frequency accuracy and stability. The
Si5348 is programmable via a serial interface with in-circuit programmable non-volatile
memory so it always powers up into a known configuration. Programming the Si5348 is
easy with
ClockBuilder Pro
™
software. Factory pre-programmed devices are also availa-
ble.
KEY FEATURES
• Three independent DSPLLs in a single
monolithic IC supporting flexible SyncE/
IEEE 1588 and SETS architectures
• Ultra-low jitter of 100 fs
• Input frequency range:
• External crystal: 48 to 54 MHz
• REF clock: 5 to 250 MHz
• Diff clock: 8 kHz to 750 MHz
• LVCMOS clock: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 1 PPS to 712.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Meets the requirements of:
• ITU-T G.8273.2 T-BC
• ITU-T G.8262 (SyncE) EEC Options 1 &
2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253
(Stratum-3/3E)
Applications:
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization
48-54 MHz XTAL
XA
OSC
IN3
IN4
IN0
IN1
IN2
÷FRAC
÷FRAC
÷FRAC
DSPLL A
Status Flags
I2C / SPI
Status Monitor
Control
NVM
DSPLL C
DSPLL D
XB
TCXO/OCXO
REFb
REF
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
Si5348
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Rev. 1.0
Si5348 Rev D Data Sheet
Feature List
1. Feature List
The Si5348 features are listed below:
• Three independent DSPLLs in a single monolithic IC support-
ing flexible SyncE/IEEE 1588 and SETS architectures
• Ultra-Low Jitter
• 100 fs typ (12 kHz to 20 MHz)
• Meets the requirements of:
• ITU-T G.8273.2 T-BC
• ITU-T G.8262 (SyncE) EEC Options 1 & 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Each DSPLL generates any output frequency from any input
frequency
• Input frequency range:
• External crystal: 48-54 MHz
• REF clock: 5-250 MHz
• Diff clock: 8 kHz-750 MHz
• LVCMOS clock: 8 kHz-250 MHz
• Output frequency range:
• Differential: 1 PPS to 712.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Pin or software controllable DCO on each DSPLL with typical
resolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/hold-
over accuracy and stability
• Programmable jitter attenuation bandwidth per DSPLL:
0.001 Hz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS,
HCSL, CML
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring: LOS, OOF, LOL
• Serial Interface: I
2
C or SPI (3-wire or 4-wire)
• ClockBuilder
TM
Pro software tool simplifies device configura-
tion
• 5 input, 7 output, 64 QFN
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Si5348 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si5348 Ordering Guide
# of
DSPLLs
3
—
—
Output Clock Frequency
Range
1 Hz to 712.5 MHz
1 Hz to 350 MHz
—
12.800 MHz
Temperature
Range
–40 to 85 °C
—
—
Ordering Part Number
Si5348A-D-GM
1, 2
Si5348B-D-GM
Si5348-D-EVB
SiOCXO1-EVB
1, 2
Package
RoHS-6, Pb-Free
64-Lead 9x9 QFN
Evaluation Board
OCXO Evaluation
Board
Yes
—
—
Note:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software.
Part number format is: Si5348A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed
configuration.
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock
family
member (7, 6)
g = Device
grade
(A, B)
Product
Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
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Si5348 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5348 offers three DSPLLs that have identical performance and flexibility which can be independently configured and controlled
through the serial interface. Each of the DSPLLs support locked, free-run, and holdover modes of operation with an optional DCO mode
for IEEE 1588 applications. The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The refer-
ence input (REF/REFb) determines the frequency accuracy and stability while in free-run and holdover modes. The external crystal
completes the internal oscillator circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs
(IN0 - IN2) for synchronizing the DSPLLs. Input selection can be manual or automatically controlled using an internal state machine.
Two additional manually selected inputs are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any
of the DSPLLs using a flexible crosspoint connection. Output 6 is the only output that can be configured for a 1 Hz output to support 1
PPS.
3.1 Standards Compliance
Each of the DSPLLs meet the requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcordia
GR-1244 and GR-253 as shown in the compliance report. The DCO feature enables IEEE1588 (PTP) implementations in addition to
hybrid SyncE + IEEE1588 (T-BC).
3.2 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division
(Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a
specific frequency plan are easily determined using the ClockBuilder Pro utility.
3.3 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop
bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,
each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
Table 3.1. Loop Bandwidth Requirements for North America
SONET (Telcordia)
GR-253 Stratum 3E
GR-253 Stratum 3
—
3.3.1 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock
acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The fastlock
feature can be enabled or disabled independently for each of the DSPLLs.
3.4 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in
Figure 3.1 Modes of Operation
on page 4.
The following sections describe each of these modes in greater detail.
SDH (ITU-T)
G.812 Type III
G.812 Type IV
G.813 Option 1
SyncE (ITU-T)
—
G.8262 EEC Option 2
G.8262 EEC Option 1
Loop Bandwidth
0.001 Hz
<0.1 Hz
1 - 10 Hz
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Si5348 Rev D Data Sheet
Functional Description
3.4.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A
soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs,
while a soft reset can either affect all or each DSPLL individually.
Power-Up
Reset and
Initialization
No valid
input clocks
selected
Free-run
Valid input clock
selected
An input is
qualified and
available for
selection
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
No valid input
clocks available
for selection
Holdover
Mode
Locked
Mode
Input Clock
Switch
Selected input
clock fails
Yes
Other Valid
Clock Inputs
No Available?
Yes
No
Holdover
History
Valid?
Figure 3.1. Modes of Operation
3.4.2 Free-run Mode
Once power is applied to the Si5348 and initialization is complete, all three DSPLLs will automatically enter freerun mode. The frequen-
cy accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the clock source at the
reference inputs (REF/REFb). A TCXO or OCXO is recommended for applications that need frequency accuracy and stability to meet
the synchronization standards as shown in the following table:
Table 3.2. Free-run Accuracy for North American and European Synchronization Standards
SONET (Telcordia)
GR-253 Stratum 3E
GR-253 Stratum 3
—
3.4.3 Lock Acquisition Mode
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process.If the fast lock feature is enabled, a DSPLL will acquire lock using
the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. Dur-
ing lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
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SDH (ITU-T)
G.812 Type III
G.812 Type IV
G.813 Option 1
SyncE (ITU-T)
—
G.8262 EEC Option 2
G.8262 EEC Option 1
Free-run Accuracy
±4.6 ppm
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