Data Sheet
INDT/R165B
INDT/R330B
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Q_DS_GigaSTaR_DDL
Long Distance Digital Display
Link Transmitter & Receiver
The GigaSTaR
Digital Display Link is an innovative
high-speed interconnect featuring simultaneous trans-
mission of digital video, audio and bi-directional side-
band data over a standard shielded twisted pair cable up
to 50 m (500 m with fiber optics). It supports VESA video
resolution standards ranging from VGA to XGA
(INDT/R165B) or to UXGA (INDT/R330B) with up to 16.7
million colors. The sideband channels provide bandwidth
up to 264 Mbps to connect peripheral components like
keyboard, mouse, disc drive and audio devices.
Features:
•
−
−
•
−
−
−
•
•
•
•
•
•
•
Supported VESA video resolutions:
INDT/R165B:
VGA
…
XGA
INDT/R330B:
VGA
…
UXGA
Flexible parallel graphics controller and LC-display
interfaces:
12-bit (½ pixel/clock) – Tx only
18- / 24-bit (1 pixel/clock)
36- / 48-bit (2 pixel/clock)
Flexible pixel data clocking on rising/falling/both
clock edges
Pixel Clock frequency: 24 – 161 MHz
Easy adaptation to DVI and LDI/LVDS through
standard interface devices
4 channel audio interface (IEC958 compliant S/P-
DIF)
High- and low-speed bi-directional sideband data
channels
Single + 3.3 V power supply
Extended temperature range: -40 – +85 °C
Applications:
•
Long distance multimedia consoles
•
High resolution industrial remote terminals
•
Video broadcast systems
•
Long distance camera links
•
Machine vision systems
•
Car navigation & telematics systems
•
Digital TV equipment
•
Video Projectors
•
Home Cinemas
Chip
Max. resolution (VESA, 60 Hz)
and max. available video bandwidth
Video, Audio,
Sideband
XGA 18-bit
SXGA 24-bit
Video, Audio
XGA 18-bit
UXGA 18-bit
Video
XGA 24-bit
UXGA 18-bit
INDT/R165B
INDT/R330B
Typical Application:
Optional Data Sources
PC
Graphics
Controller
Camera
DVD
HDTV
DATA
AUDIO
VIDEO
Transmitter
Receiver
VIDEO
TFT
LC-Display
INDT165B
or
INDT330B
STP-cable
INDR165B
or
INDR330B
DATA
AUDIO
Date: 2005-02-18 Revision: 1.1
Page 1 of 41
Data Sheet
INDT/R165B
INDT/R330B
Index
1.
General Description ............................................................................................................................ 3
1.1
Link Interface ....................................................................................................................................3
1.1.1
Link Interface Bandwidth ............................................................................................................3
1.2
Pixel Interface ...................................................................................................................................4
1.2.1
General Information....................................................................................................................4
1.2.2
Pixel Interface Modes .................................................................................................................5
1.2.3
Pixel Clock Sampling Modes ......................................................................................................5
1.2.4
Pixel Data I/O Color Bit Mapping ................................................................................................7
1.3
Sideband Interface ............................................................................................................................8
1.3.1
General Information....................................................................................................................8
1.3.2
Low-speed Upstream Sideband Data Channel (SB0)..................................................................9
1.3.3
High-speed Upstream Sideband Data Channel (SB1).................................................................9
1.3.4
Low-speed Downstream Sideband Data Channel (SB2) .............................................................9
1.3.5
High-speed Downstream Sideband Data Channel (SB3, SB4). ...................................................9
1.3.6
Sideband Interface Signals.......................................................................................................10
1.4
Audio Interface................................................................................................................................11
Device Configuration ........................................................................................................................ 12
2.1
Configuration Vectors and Configuration Data .................................................................................12
2.2
Configuration Process and Timing ...................................................................................................13
2.3
Interface Configuration Scheme ......................................................................................................14
2.4
Error Handling and Reset (INDR330 only) .......................................................................................15
Electrical Specification ..................................................................................................................... 16
3.1
External Circuits ..............................................................................................................................16
3.1.1
External Loop Filter Specification..............................................................................................16
3.1.2
Serial Transmission Cable Interconnect....................................................................................16
3.1.3
Serial Transmission Cable Termination.....................................................................................17
3.1.4
Receiver Equalizer ...................................................................................................................17
3.1.5
Reference Clock.......................................................................................................................17
3.1.6
V
REF
Reference Circuitry...........................................................................................................17
3.2
Power Supply..................................................................................................................................17
3.3
Absolute Maximum Ratings .............................................................................................................18
3.4
Recommended Operating Conditions ..............................................................................................18
3.5
AC–Characteristics (under recommended operating conditions, Reference Clock Freq. = 66 MHz)..19
3.6
DC–Characteristics (under recommended operating conditions) ......................................................19
3.7
Reference Clock Specification (Ta = -40 to 85° C; Vcc = 3.15 to 3.45 V)..........................................19
3.8
Timing Specification ........................................................................................................................20
Signals............................................................................................................................................... 27
4.1
INDT165B Transmitter Signal Description........................................................................................27
4.2
INDR165B Receiver Signal Description ...........................................................................................28
4.3
INDT330B Transmitter Signal Description........................................................................................30
4.4
INDR330B Receiver Signal Description ...........................................................................................32
Pin Assignment ................................................................................................................................. 34
5.1
INDT165B Transmitter ....................................................................................................................34
5.2
INDR165B Receiver ........................................................................................................................35
5.3
INDT330B Transmitter ....................................................................................................................36
5.4
INDR330B Receiver ........................................................................................................................37
Package Information ......................................................................................................................... 38
6.1
INDT/R165B....................................................................................................................................38
6.2
INDT/R330B....................................................................................................................................39
GigaSTaR Digital Display Link Evaluation Kit................................................................................ 40
Ordering and Product Availability .................................................................................................... 40
Revision History................................................................................................................................ 41
Page 2 of 41
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4
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Date: 2005-02-18 Revision: 1.1
Data Sheet
INDT/R165B
INDT/R330B
1. General Description
The GigaSTaR
Digital Display Link is a high-speed serial and long distance link for video, audio and digital data, which
supports the popular VESA standard but also proprietary video formats from VGA to UXGA with color depth up to 24 bits.
1.1
Link Interface
The INDT/R165B link requires one single twisted pair cable for the high-speed downlink. The INDT/R330B provides double
bandwidth by using two twisted pairs. Both devices offer an uplink connection using a twisted pair. The downlink must be
established before the uplink can be activated.
VIDEO
M
U
X
Downlink
AUDIO
Only INDT/R330
D
E
M
U
X
VIDEO
AUDIO
SIDEBAND
DATA
Uplink
SIDEBAND
DATA
Figure 1.1: GigaSTaR Digital Display Link Interfaces
The transmitter’s and receiver’s generic parallel RGB interfaces (CMOS/TTL compatible) support direct connection to the
parallel data port of any graphic controller or to any flat panel display with a parallel pixel data port. The bit width of the
pixel data path can be scaled to support the 18- or 24-bit mode with 1 pixel/clock, the 36- or 48-bit mode with 2 pixel/clock,
or the 12-bit mode with ½ pixel/clock. Pixel data can be clocked into the transmitter on the rising, falling or on both edges
(only 12-, 18-, 24-bit mode) of the pixel clock. Pixel data are provided at the receiver on the rising, falling or on both edges
(only 18-, 24-bit mode) of the pixel clock.
1.1.1
Link Interface Bandwidth
The bandwidth of the downlink is shared between video, audio and sideband data. Disabling audio and/or sideband
channels, even partially, increases the available bandwidth for the video data. The video configuration required for VESA
standard compatible video resolutions is shown in
Table 1.1
and
Table 1.2.
Mode
1
2
3
INDT/R165B configurations
High-speed
Low-speed
Audio
Sideband
Sideband
X
X
X/–
–
X
X
–
–
–
Up to
VESA-Mode
XGA 18 color bits
XGA 18 color bits
XGA 24 color bits
Table 1.1: INDT/R165B Video Configuration
Date: 2005-02-18 Revision: 1.1
Page 3 of 41
Data Sheet
INDT/R165B
INDT/R330B
Up to
VESA-Mode
SXGA 24 color bits
UXGA 18 color bits
UXGA 18 color bits
Mode
1
2
3
INDT/R330B configurations
High-speed
Low-speed
Audio
Sideband
Sideband
X
X
X
/
–
–
X
X
–
–
–
Table 1.2: INDT/R330B Video Configuration
Note:
Implementation of video modes other than VESA is possible. Special modes may need evaluation.
1.2
1.2.1
Pixel Interface
General Information
The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as
graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also
be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI.
PX_CLK+
PX_CLK–
PX_D[47:0]
48
PX_HSYNC
PX_VSYNC
PX_DE
PX_CLK+
Video
Downstream
Video
PX_D[47:0]
48
PX_HSYNC
PX_VSYNC
PX_DE
INDT
Transmitter
INDR
Receiver
Figure 1.2: Pixel Interface
Signal
PX_D[47:0]
PX_CLK+
PX_CLK–
PX_HSYNC
PX_VSYNC
PX_DE
Tx
IN
IN
IN
IN
IN
IN
1
Rx
OUT
OUT
OUT
OUT
OUT
OUT
Description
Configurable parallel pixel data interface
Pixel clock 24 – 161 MHz, diff + or single-ended
Pixel clock 24 – 161 MHz, diff –
Pixel data framing – Horizontal sync pulse
Pixel data framing – Vertical sync pulse
Pixel data framing – Data enable
Table 1.3: Pixel Interface Signals
1
Configurable to 3.3V or 1.8V input levels via
V
REF
-
pin
.
Page 4 of 41
Date: 2005-02-18 Revision: 1.1
Data Sheet
INDT/R165B
INDT/R330B
The transmitter’s pixel interface accept pixel data with a pixel clock frequency of 24 – 161 MHz (full pixel mode). In single-
ended mode, PX_CLK+ is the clock input and PX_CLK– has to be tied to GND. All pixel data and pixel clock inputs of the
transmitter can be selected through the V
REF
-pin to either work with conventional graphic controllers with 3.3 V output
voltage swing or to work with latest controllers with low voltage swing (1.0 – 2.0 V, see
Figure 3.3 VREF Reference
Circuitry).
The pixel data and pixel clock outputs of the receiver provide a 3.3 V CMOS compliant output.
1.2.2
Pixel Interface Modes
The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of
the pixel interface is a function of the selected operating mode.
•
In
half-pixel mode
the bit width of the pixel interface is
12-bit.
In half-pixel mode the lower and upper 12 bits of a parallel
video interface (24-bit) are transmitted at consecutive sampling edges. This mode is supported only at the Tx devices.
•
In
full-pixel mode
the bit width of the pixel interface can be set to support an
18- or 24-bit
wide parallel video interface.
1 pixel per sampling edge is transmitted.
•
In
double-pixel mode
the bit width of the pixel interface can be set to support a
36- or 48-bit
wide parallel video
interface. 2 pixels per sampling edge are transmitted.
1.2.3
Pixel Clock Sampling Modes
The pixel interface can be set to support data sampling at the
rising, falling
or at
both edges
of the pixel clock,
depending on the selected mode.
Table 1.4
and
Figure 1.3, Figure 1.4, Figure 1.5
summarize the various options for configuring the pixel interface.
Pixel Mode
Clock
Edge
PX_CLK+
PX_CLK
Description
both
12-bit
(Half Pixel)
TX Only
both
rising
rising
18-bit
(Full Pixel)
24-bit
(Full Pixel)
36-bit
(Double
Pixel)
48-bit
(Double
Pixel)
rising
falling
both
rising
falling
both
rising
falling
rising
falling
↑↓
↑↓
↑
↑
↑
↓
↑↓
↑
↓
↑↓
↑
↓
↑
↓
–
–
↑
↑
–
–
–
–
–
–
–
–
–
–
12 bits low part of pixel(n) @ rising edge of PX_CLK+
12 bits high part of pixel(n) @ falling edge of PX_CLK+
12 bits low part of pixel(n) @ falling edge of PX_CLK+
12 bits high part of pixel(n) @ rising edge of PX_CLK+
12 bits low part of pixel(n) @ rising edge of PX_CLK+
12 bits high part of pixel(n) @ rising edge of PX_CLK
12 bits low part of pixel(n) @ rising edge of PX_CLK
12 bits high part of pixel(n) @ rising edge of PX_CLK+
18 bits of pixel(n) sampled at rising edge of PX_CLK+
18 bits of pixel(n) sampled at falling edge of PX_CLK+
18 bits of pixel(n) sampled at both edges of PX_CLK+
24 bits of pixel(n) sampled at rising edge of PX_CLK+
24 bits of pixel(n) sampled at falling edge of PX_CLK+
24 bits of pixel(n) sampled at both edges of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Table 1.4: Overview – Pixel Interface Configurations
Date: 2005-02-18 Revision: 1.1
Page 5 of 41
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