IS61NLP12836A-250B3I datasheet, PDF

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

ISSI

OCTOBER 2006

®

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

NVP: V

DD

2.5V (± 5%), V

DDQ

2.5V (± 5%)

NLP: V

DD

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

• Industrial temperature available

• Lead-free available

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 128K words by 32 bits, 128K words by 36 bits,

and 256K words by 18 bits, fabricated with

ISSI

's advanced

CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

WE

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

t

KQ

t

KC

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

4

250

-200

3.1

5

200

Units

ns

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. A

10/03/06

1

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

BLOCK DIAGRAM

ISSI

A2-A16 or A2-A17

128Kx32;

128Kx36;

256Kx18

MEMORY ARRAY

®

x 32/x 36: A [0:16] or

x 18: A [0:17]

ADDRESS

REGISTER

MODE

A0-A1

BURST

ADDRESS

COUNTER

A'0-A'1

K

DATA-IN

REGISTER

CLK

CKE

CE

CE2

ADV

WE

BWŸ

X

OE

ZZ

CONTROL

LOGIC

K

WRITE

ADDRESS

REGISTER

WRITE

ADDRESS

REGISTER

K

DATA-IN

REGISTER

}

CONTROL

REGISTER

CONTROL

LOGIC

K

OUTPUT

REGISTER

BUFFER

(X=a,b,c,d or a,b)

32, 36 or 18

DQx/DQPx

2

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. A

10/03/06

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

ISSI

®

Bottom View

165-Ball, 13 mm x 15mm BGA

1 mm Ball Pitch, 11 x 15 Ball Array

Bottom View

119-Ball, 14 mm x 22 mm BGA

1 mm Ball Pitch, 7 x 17 Ball Array

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. A

10/03/06

3

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

PIN CONFIGURATION — 128K

X

36, 165-Ball PBGA (TOP VIEW)

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

NC

DQPc

DQc

NC

DQd

DQPd

NC

MODE

2

A

NC

DQc

NC

DQd

NC

3

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

4

BWc

BWd

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

5

BWb

BWa

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

6

CE2

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1*

A0*

7

CKE

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

8

ADV

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

9

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

ISSI

10

A

NC

DQb

NC

DQa

NC

A

11

NC

DQPb

DQb

ZZ

DQa

DQPa

NC

A

®

Note:

A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A

A0, A1

ADV

WE

CLK

CKE

BWx

(x=a-d)

OE

ZZ

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

Synchronous Read/Write Control

Input

Synchronous Clock

Clock Enable

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

MODE

V

DD

NC

DQx

DQPx

V

DDQ

V

SS

Burst Sequence Selection

3.3V/2.5V Power Supply

No Connect

Data Inputs/Outputs

Parity Data I/O

Isolated output Power Supply

3.3V/2.5V

Ground

CE, CE2,

CE2 Synchronous Chip Enable

4

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. A

10/03/06

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

119-PIN PBGA PACKAGE CONFIGURATION

1

2

3

ISSI

128K x 36 (TOP VIEW)

4

5

6

7

®

A

B

C

D

E

F

V

DDQ

NC

DQc

V

DDQ

DQc

V

DDQ

DQd

V

DDQ

DQd

NC

V

DDQ

A

CE2

A

DQPc

DQc

V

DD

DQd

DQPd

A

NC

A

V

SS

V

SS

V

SS

BWc

V

SS

NC

V

SS

BWd

V

SS

V

SS

V

SS

MODE

A

NC

ADV

V

DD

NC

CE

OE

NC

WE

V

DD

CLK

NC

CKE

A

1

*

A

0

*

V

DD

A

NC

A

Vss

BWb

Vss

NC

Vss

BWa

Vss

NC

A

NC

A

CE2

A

DQPb

DQb

V

DD

DQa

DQPa

A

NC

V

DDQ

NC

DQb

V

DDQ

DQb

V

DDQ

DQa

V

DDQ

DQa

NC

ZZ

V

DDQ

G

H

J

K

L

M

N

P

R

T

U

Note:

A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A

A0, A1

ADV

WE

CLK

CKE

CE

CE2

BWx

(x=a-d)

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

Synchronous Read/Write Control Input

Synchronous Clock

Clock Enable

Synchronous Chip Select

Synchronous Byte Write Inputs

OE

ZZ

MODE

V

DD

V

SS

NC

DQa-DQd

DQPa-Pd

V

DDQ

Output Enable

Power Sleep Mode

Burst Sequence Selection

Power Supply

Ground

No Connect

Data Inputs/Outputs

Parity Data I/O

Output Power Supply

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. A

10/03/06

5

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.46 V
Minimum supply/operating voltage	3.14 V
Rated supply voltage	3.3 V
maximum access time	3.1 ns
Processing package description	LEAD FREE, TQFP-100
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	FLATPACK, LOW PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.6500 mm
terminal coating	MATTE TIN
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	18
organize	256K X 18
storage density	4.72E6 deg
operating mode	SYNCHRONOUS
Number of digits	262144 words
Number of digits	256K
Memory IC type	ZBT SRAM
serial parallel	PARALLEL

IS61NLP12836A-250B3I

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