Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 8
Chapter 2. Functional Description ...................................................................................................... 10
Block Diagrams ................................................................................................................................................... 10
Convolutional Interleaver/de-interleaver .................................................................................................... 11
Rectangular Interleaver/De-interleaver ...................................................................................................... 12
Latency....................................................................................................................................................... 13
Signal Descriptions ............................................................................................................................................. 13
Timing Diagrams ................................................................................................................................................. 16
Chapter 3. Parameter Settings ............................................................................................................ 17
Type and Mode Tab ............................................................................................................................................ 18
Type ........................................................................................................................................................... 18
Mode .......................................................................................................................................................... 18
Convolutional Parameters Tab............................................................................................................................ 19
Interleaver/Deinterleaver............................................................................................................................ 19
Rectangular Parameters Tab .............................................................................................................................. 20
Interleaver/Deinterleaver............................................................................................................................ 20
Block Size Type ......................................................................................................................................... 20
Permutations .............................................................................................................................................. 21
Convolutional Optional Pins Tab......................................................................................................................... 21
Rectangular Optional Pins Tab ........................................................................................................................... 22
Chapter 4. IP Core Generation............................................................................................................. 24
Licensing the IP Core.......................................................................................................................................... 24
Getting Started .................................................................................................................................................... 24
IPexpress-Created Files and Top Level Directory Structure............................................................................... 26
Permutation Pattern Input File Format ................................................................................................................ 28
Instantiating the Core .......................................................................................................................................... 28
Running Functional Simulation ........................................................................................................................... 28
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 29
Hardware Evaluation........................................................................................................................................... 30
Enabling Hardware Evaluation in Diamond................................................................................................ 30
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 30
Updating/Regenerating the IP Core .................................................................................................................... 30
Regenerating an IP Core in Diamond ........................................................................................................ 30
Regenerating an IP Core in ispLEVER ...................................................................................................... 31
Chapter 5. Support Resources ............................................................................................................ 32
Lattice Technical Support.................................................................................................................................... 32
Online Forums............................................................................................................................................ 32
Telephone Support Hotline ........................................................................................................................ 32
E-mail Support ........................................................................................................................................... 32
Local Support ............................................................................................................................................. 32
Internet ....................................................................................................................................................... 32
References.......................................................................................................................................................... 32
LatticeEC/ECP ........................................................................................................................................... 32
LatticeECP2/M ........................................................................................................................................... 32
LatticeECP3 ............................................................................................................................................... 32
LatticeSC/M................................................................................................................................................ 32
LatticeXP.................................................................................................................................................... 33
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Interleaver/De-interleaver IP Core User’s Guide
Lattice Semiconductor
Table of Contents
LatticeXP2.................................................................................................................................................. 33
Revision History .................................................................................................................................................. 33
Appendix A. Resource Utilization ....................................................................................................... 34
LatticeECP3 FPGAs............................................................................................................................................ 34
Ordering Part Number................................................................................................................................ 34
LatticeECP and LatticeEC FPGAs ...................................................................................................................... 34
Ordering Part Number................................................................................................................................ 34
LatticeECP2 Devices .......................................................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
LatticeECP2M Devices ....................................................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
LatticeXP Devices ............................................................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
LatticeXP2 Devices ............................................................................................................................................. 36
Ordering Part Number................................................................................................................................ 36
LatticeSC/M Devices........................................................................................................................................... 36
Ordering Part Number................................................................................................................................ 36
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Interleaver/De-interleaver IP Core User’s Guide
Chapter 1:
Introduction
Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such
as burst error or fading. The interleaver rearranges input data such that consecutive data are spaced apart. At the
receiver end, the interleaved data is arranged back into the original sequence by the de-interleaver. As a result of
interleaving, correlated noise introduced in the transmission channel appears to be statistically independent at the
receiver and thus allows better error correction.
The Lattice Interleaver/de-interleaver IP core supports rectangular block type and convolutional architectures.
Rectangular interleaving arranges the input data row-wise in a matrix. The interleaved data is obtained by reading
the columns of the matrix. Convolutional interleaving feeds the input data to a number of branches, each of which
has a shift register with pre-defined length. The output data is taken from the branch outputs. Lattice’s Convolu-
tional Interleaver/de-interleaver IP Cores are compliant with ATSC and DVB standards, while the Rectangular Inter-
leaver/de-interleaver is compliant with IEEE 802.16a standard.
Quick Facts
Table 1-1
through
Table 1-9
give quick facts about the Interleaver/de-interleaver IP core for LatticeEC™, Lat-
ticeECP™, LattceECP2™, LatticeECP2M™, LatticeECP3™, LatticeSC™, LatticeSCM™, LatticeXP™, and
LatticeXP2™ devices, respectively.
Table 1-1. Interleaver/De-interleaver IP Core for LatticeEC Devices Quick Facts
Interleaver/de-interleaver IP Configuration
Convolutional
Interleaver
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
200
2
200
2
200
Lattice Diamond™ 1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify™ Pro for Lattice D-2009.12L-1
Aldec
®
Active-HDL™ 8.2 Lattice Edition
Mentor Graphics ModelSim™ SE 6.3F
Convolutional
De-interleaver
LFEC3E
LFEC20E-5F672C
100
4
100
4
Rectangular
Interleaver
Rectangular
De-interleaver
LatticeEC
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Interleaver/De-interleaver IP Core User’s Guide
Lattice Semiconductor
Table 1-2. Interleaver/De-interleaver IP Core for LatticeECP Devices Quick Facts
Introduction
Interleaver/de-interleaver IP Configuration
Convolutional
Interleaver
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
200
2
200
2
200
Lattice Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Convolutional
De-interleaver
Rectangular
Interleaver
Rectangular
De-interleaver
LatticeECP
LFECP6E
LFECP20E-5F672C
100
4
100
4
Table 1-3. Interleaver/De-interleaver IP Core for LatticeECP2 Devices Quick Facts
Interleaver/de-interleaver IP Configuration
Convolutional
Interleaver
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
200
1
200
1
200
Lattice Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Convolutional
De-interleaver
Rectangular
Interleaver
Rectangular
De-interleaver
LatticeECP2
LFE2-6E
LFE2-50E-7F672C
100
2
100
2
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Interleaver/De-interleaver IP Core User’s Guide
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