KAI-1020
1000 (H) x 1000 (V) Interline
CCD Image Sensor
Description
The KAI−1020 Image Sensor is a one megapixel interline CCD with
integrated clock drivers and on-chip correlated double sampling.
The progressive scan architecture and global electronic shutter
provide excellent image quality for full motion video and still image
capture.
The integrated clock drivers allow for easy integration with CMOS
logic timing generators. The sensor features a fast line dump for
high-speed sub-window readout and single (30 fps) or dual (48 fps)
output operation.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Number of Outputs
Pixel Size
Active Image Size
Typical Value
Interline CCD, Progressive Scan
1028 (H)
×
1008 (V)
1004 (H)
×
1004 (V)
1000 (H)
×
1000 (V)
1 or 2
7.4
mm
(H)
×
7.4
mm
(V)
7.4 mm (H)
×
7.4 mm (V)
10.5 mm (Diagonal)
2/3″ Optical Format
1:1
40,000 e
−
12
mV/e
−
44%
33%, 39%, 41%
39%, 42%, 44%
50 e
−
rms
< 0.5 nA/cm
2
58 dB
100 X
< 10 e
−
< 0.03%
40 MHz/Channel (2 Channels)
30 fps
48 fps
49 fps
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Figure 1. KAI−1020 Interline
CCD Image Sensor
Features
•
10-Bits Dynamic Range at 40 MHz
•
Large 7.4
mm
Square Pixels for High
•
•
•
•
•
•
•
•
•
•
•
•
Sensitivity
Progressive Scan (Non-Interlaced)
Integrated Correlated Double Sampling
(CDS) Up to 40 MHz
Integrated Electronic Shutter Driver
Reversible HCCD Capable of 40 MHz
Operation All Timing Inputs 0 to 5 V
Single or Dual Video Output Operation
Progressive Scan or Interlaced
Fast Dump Gate for High Speed
Sub-Window Readout
Anti-Blooming Protection
Aspect Ratio
Saturation Signal
Output Sensitivity
Quantum Efficiency
ABA (500 nm)
CBA (620 nm, 540 nm, 460 nm)
FBA (600 nm, 540 nm, 460 nm)
Dark Noise
Dark Current (Typical)
Dynamic Range
Blooming Suppression
Image Lag
Smear
Maximum Data Rate
Frame Rate
Progressive Scan, One Output
Progressive Scan, Dual Outputs
Interlaced Scan, One Output
Integrated Vertical Clock Driver
Applications
Machine Vision
Medical
Scientific
Surveillance
ORDERING INFORMATION
Integrated Correlated Double Sampling (CDS)
Integrated Electronic Shutter Driver
Package
Cover Glass
68 Pin PGA or 64 Pin CLCC
AR Coated, 2 Sides
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
©
Semiconductor Components Industries, LLC, 2015
1
October, 2015 − Rev. 4
Publication Order Number:
KAI−1020/D
KAI−1020
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−1020 IMAGE SENSOR
Part Number
KAI−1020−AAA−JP−BA
KAI−1020−ABB−FD−AE
KAI−1020−ABB−FD−BA
KAI−1020−ABB−JP−AE
KAI−1020−ABB−JP−BA
KAI−1020−ABB−JB−AE
KAI−1020−ABB−JB−BA
KAI−1020−ABB−JD−AE
KAI−1020−ABB−JD−BA
KAI−1020−FBA−FD−AE
KAI−1020−FBA−FD−BA
KAI−1020−FBA−JD−AE
KAI−1020−FBA−JD−BA
KAI−1020−CBA−FD−AE*
KAI−1020−CBA−FD−BA*
KAI−1020−CBA−JD−AE*
KAI−1020−CBA−JD−BA*
Description
Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, No Coatings, Standard Grade
Monochrome, Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Monochrome, Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Sample
Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Standard Grade
Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass (No Coatings), Engineering Sample
Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass (No Coatings), Standard Grade
Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1020CM
Serial Number
KAI−1020−FBA
Serial Number
KAI−1020−ABB
Serial Number
Marking Code
KAI−1020
Serial Number
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KAI−1020−12−40−A−EVK
Evaluation Board (Complete Kit)
Description
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−1020
DEVICE DESCRIPTION
Architecture
2 Buffer Rows
B
G
G R
B
G
G R
12 Dark Columns
1000 (H)
y
1000 (V)
Active Pixels
Pixel 1,1
8 Empty Pixels
B
G
G R
B
G
G R
12 Dark Columns
8 Empty Pixels
VOUT2
12
12
8
8
2 Buffer Columns
2 Buffer Rows
4 Dark Rows
Fast Line Dump
VOUT1
8
Single
or
Dual Output
8
12
12
2
2
500
1000
500
Figure 2. Block Diagram
There are 4 light shielded rows followed 1004 photoactive
rows. The first 2 and the last 2 photoactive rows are buffer
rows giving a total of 1000 lines of image data.
In the single output mode all pixels are clocked out of the
Video 1 output in the lower left corner of the sensor. The first
8 empty pixels of each line do not receive charge from the
vertical shift register. The next 12 pixels receive charge from
the left light-shielded edge followed by 1004
photo-sensitive pixels and finally 12 more light shielded
pixels from the right edge of the sensor. The first and last 2
photosensitive pixels are buffer pixels giving a total of 1000
pixels of image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out Video 1 and the right half of the image is clocked
out Video 2. Each row consists of 8 empty pixels followed
by 12 light shielded pixels followed by 502 photosensitive
pixels. When reconstructing the image, data from Video 2
will have to be reversed in a line buffer and appended to the
Video 1 data.
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3
2 Buffer Columns
2
2
KAI−1020
Physical Description
Pin Description and Device Orientation
Pin Grid Array
When viewed from the top with the pin 1 index to the
upper left, the center of the photoactive pixel array is offset
0.006″ above the physical center of the package. The pin 1
index is located in the corner of the package above pins L2
and K1. When operated in single output mode the first pixel
out of the sensor will be in the corner closest to VOUT1B
(pin L9). The HCCD is parallel to the row of pins A10 to
L10. In the pictures below, the VCCD transfers charge
down.
Figure 3. Pin 1 Location
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4
KAI−1020
Pin Grid Array Pin Description
Pin 1 Index
K1
J1
H1
G1
F1
E1
D1
C1
B1
VSUB
L2
V2IN
K2
J2
H2
G2
F2
E2
D2
C2
B2
V1IN
A2
V2OUT
L3
V2LOW
K3
SH
B3
VSH15
A3
V2HIGH
L4
V2MID
K4
SHC2
B4
SHC1
A4
VSUB
L5
V2A
K5
V1LOW
B5
SHD1C1
A5
V2S5
L6
V2S9
K6
V1OUT
B6
A6
FD
L7
V2B
K7
V1S5
B7
V1MID
A7
VOUT1A
L8
VDD
K8
VDD
B8
V1
A8
VOUT1B
L9
GND
K9
GND
B9
VOUT2A
A9
VDD
L10
K10
R1
J10
S1B
H10
H1BL
G10
H2S
F10
GND
E10
H2BR
D10
S2A
C10
VDD
B10
VOUT2B
A10
T1
K11
S1A
J11
H2BL
H11
GND
G11
H1S
F11
H1BR
E11
S2B
D11
R2
C11
T2
B11
Figure 4. PGA Package Pin Description (Top View)
Table 4. PIN DESCRIPTION
Pin
K2
L2
K3
L3
K4
L4
K5
L5
K6
L6
K7
L7
Label
V2IN
VSUB
V2LOW
V2OUT
V2MID
V2HIGH
fV2A
VSUB
V2S9
V2S5
fV2B
fFD
VCCD Gate Phase 2 Input
Substrate Voltage Input
VCCD Phase 2 Clock Driver Low
VCCD Phase 2 Clock Driver Output
VCCD Phase 2 Clock Driver Mid
VCCD Phase 2 Clock Driver High
VCCD Phase 2 Clock Driver Input A
Substrate Voltage Input
VCCD Phase 2 Clock Driver +9 V
VCCD Phase 2 Clock Driver +5 V Fast Dump Clock Driver +5 V
VCCD Phase 2 Clock Driver Input B
Fast Dump Clock Driver Input
Function
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