AT45DQ161
16-Mbit DataFlash, 2.3V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support
Features
Single 2.3V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
™
Supports RapidS operation
Supports Dual-input and Quad-input Buffer Write
Supports Dual-output and Quad-output Read
Very high operating frequencies
85MHz (for SPI)
85MHz (for Dual-I/O and Quad-I/O)
Clock-to-output time (t
V
) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the main memory array
Flexible programming options
Byte/Page Program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible erase options
Page Erase (512/528 bytes), Block Erase (4KB)
Sector Erase (128KB), Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
500nA Ultra-Deep Power-Down current (typical)
3µA Deep Power-Down current (typical)
25µA Standby current (typical)
11mA Active Read current (typical at 20MHz)
Endurance: 100,000 program/erase cycles per page minimum (50,000 cycles
for extended temperature option)
Data retention: 20 years
Complies with full industrial temperature range (extended temperature optional)
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide and 0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)
8790E–DFLASH–1/2017
Description
The AT45DQ161 is a 2.3V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of
digital voice, image, program code, and data storage applications. The AT45DQ161 also supports Dual-I/O, Quad-I/O
and the RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are
organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DQ161 also contains
two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being
reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data
stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E
2
PROM emulation
(bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash
®
uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces
active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and
reduces package size. The device is optimized for use in many commercial and industrial applications where high-
density, low-pin count, low-voltage, and low-power are essential.
To allow for simple in-system re-programmability, the AT45DQ161 does not require high input voltages for programming.
The device operates from a single 2.3V to 3.6V power supply for the erase and program and read operations. The
AT45DQ161 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial
Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
1.
Pin Configurations and Pinouts
Figure 1-1. Pinouts
8-lead SOIC
Top View
SI
(I/O
0
)
SCK
RESET
(I/O
3
)
CS
1
2
3
4
8
7
6
5
SO
(I/O
1
)
GND
V
CC
WP
(I/O
2
)
SI (I/O
0
)
SCK
RESET (I/O
3
)
CS
8-pad UDFN
Top View
1
2
3
4
9-ball UBGA
Top View
SO (I/O
1
)
7
GND
6
V
CC
8
5
SCK
GND
V
CC
WP (I/O
2
)
CS
NC
WP
SO
SI
RST
Note:
1.
The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.
This pad can be a “no connect” or connected to GND.
AT45DQ161
8790E–DFLASH–1/2017
2
Table 1-1.
Symbol
Pin Configurations
Name and Function
Chip Select:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not Deep Power-Down
mode) and the output pin (SO) will be in a high-impedance state. When the device is
deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such
as a program or erase cycle, the device will not enter the standby mode until the completion of
the operation.
Serial Clock:
This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is
always latched on the rising edge of SCK, while output data on the SO pin is always clocked
out on the falling edge of SCK.
Serial Input (I/O
0
):
The SI pin is used to shift data into the device. The SI pin is used for all
data input including command and address sequences. Data on the SI pin is always latched on
the rising edge of SCK.
With the Dual-output and Quad-output Read Array commands, the SI pin becomes an output
pin (I/O
0
) and, along with other pins, allows two bits (on I/O
1-0
) or four bits (on I/O
3-0
) of data to
be clocked out on every falling edge of SCK. To maintain consistency with SPI nomenclature,
the SI (I/O
0
) pin will be referenced as SI throughout the document with exception to sections
dealing with the Dual-output and Quad-output Read Array commands in which it will be
referenced as I/O
0
.
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
Serial Output (I/O
1
):
The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-output and Quad-output Read Array commands, the SO pin is used as an output
pin (I/O
1
) in conjunction with other pins to allow two bits (on I/O
1-0
) or four bits (on I/O
3-0
) of data
to be clocked out on every falling edge of SCK. To maintain consistency with SPI
nomenclature, the SO (I/O
1
) pin will be referenced as SO throughout the document with
exception to sections dealing with the Dual-output and Quad-output Read Array commands in
which it will be referenced as I/O
1
.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
Input/
Output
Asserted
State
Type
CS
Low
Input
SCK
—
Input
SI (I/O
0
)
—
SO (I/O
1
)
—
Input/
Output
AT45DQ161
8790E–DFLASH–1/2017
3
Table 1-1.
Symbol
Pin Configurations (Continued)
Name and Function
Write Protect (I/O
2
):
When the WP pin is asserted, all sectors specified for protection by the
Sector Protection Register will be protected against program and erase operations regardless
of whether the Enable Sector Protection command has been issued or not. The WP pin
functions independently of the software controlled protection method. After the WP pin goes
low, the contents of the Sector Protection Register cannot be modified.
The WP pin must be driven at all times or pulled-high using an external pull-up resistor.
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle
state once the CS pin has been deasserted. The Enable Sector Protection command and the
Sector Lockdown command, however, will be recognized by the device when the WP pin is
asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected to
V
CC
whenever possible.
With the Quad-output Read Array command, the WP pin becomes an output pin (I/O
2
) and,
when used with other pins, allows four bits (on I/O
3-0
) of data to be clocked out on every falling
edge of SCK. The QE bit in the Configuration Register must be set in order for the WP pin to
be used as an I/O data pin.
Asserted
State
Type
WP (I/O
2
)
Low
Input/
Output
Reset (I/O
3
):
A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset condition as
long as a low level is present on the RESET pin. Normal operation can resume once the
RESET pin is brought back to a high level.
RESET
(I/O
3
)
With the Quad-output Read Array command, the RESET pin becomes an output pin (I/O
3
) and,
when used with other pins, allows four bits (on I/O
3-0
) of data to be clocked out on every falling
edge of SCK. The QE bit in the Configuration Register must be set in order for the RESET pin
to be used as an I/O data pin.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature is not utilized, then it is
recommended that the RESET pin be driven high externally.
V
CC
GND
Device Power Supply:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
Ground:
The ground reference for the power supply. GND should be connected to the system
ground.
—
—
Power
Ground
Input/
Low
Output
AT45DQ161
8790E–DFLASH–1/2017
4
2.
Block Diagram
Figure 2-1. Block Diagram
WP
(I/O
2
)
Page (512/528 bytes)
Flash Memory Array
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
SCK
CS
RESET
(I/O
3
)
V
CC
GND
SI
(I/O
0
)
I/O Interface
SO
(I/O
1
)
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
AT45DQ161
8790E–DFLASH–1/2017
5
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