DATASHEET
CLOCK DISTRIBUTION CIRCUIT
Description
The IDT6P30006A is a low-power, eight output clock
distribution circuit. The device takes a TCXO or LVCMOS
input and generates eight high-quality outputs.
It includes a redundant input with automatic glitch-free
switching when the primary reference is removed. The
primary input may be selected by the user by pulling the
SEL pin low or high. If the primary input is removed and
brought back, it will not be re-selected until 1024 cycles
have passed.
The IDT6P30006A specifically addresses the needs of
handheld applications in both performance and package
size. The device is packaged in a small 4mm x 4mm 24-pin
QFN, allowing optimal use for limited board space.
IDT6P30006A
Features
•
•
•
•
•
Packaged in 24-pin QFN
LVCMOS or TCXO sine wave input
+1.8 V operating voltage
Glitch-free input switching
Eight buffered square wave outputs at 1.8 V LVCMOS
levels
•
Individual output enables controlled via I
2
C or OEx
•
Pb free, RoHS compliant package
•
Industrial temperature range (-40°C to +85°C)
Block Diagram
VDD 1.8 V
4
OE1
OUT1
SCLK
SDATA
OE2
OUT2
OE3
OUT3
OE4
OUT4
LVCMOS_INB
OUT5
OUT6
TCXO_INA
±100mVpp
MUX
OUT7
OUT8
3
SEL
GND
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6P30006A REV D 061711
IDT6P30006A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
Pin Assignment
TCXO_INA
GND
OUT1
OUT2
SEL Pin Configuration Table
SEL
VDD
Primary Input
LVCMOS_INB
TCXO_INA
VDD
0
1
OUT3
OUT4
GND
VDD
LVCMOS_INB
OE4
OE1
SCLK
SDATA
SEL
GND
1
19
OE Pin Configuration Table
OEx
0
1
OUTx
Disabled
Enabled
13
7
OE3
OUT7
24- pin QFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
OE4
OE1
SCLK
SDATA
SEL
GND
OE2
OUT8
VDD
OUT7
OUT6
OUT5
OE3
LVCMOS_INB
VDD
GND
OUT8
OUT6
Pin
Type
Input
Input
Input
I/O
Input
Power
Input
Output
Power
Output
Output
Output
Input
Input
Power
Power
OUT5
VDD
OE2
Pin Description
Output enable control for OUT4. Internal pull-up resistor. See table above.
Output enable control for OUT1. Internal pull-up resistor. See table above.
I
2
C clock input.
I
2
C data input.
Select pin for primary inputs. See table above. Internal pull-up resistor.
Connect to ground.
Output enable control for OUT2. Internal pull-up resistor. See table above.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Connect to +1.8 V.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Output enable control for OUT3. Internal pull-up resistor. See table above.
Connect to 13 MHz LVCMOS clock input. See table above.
Connect to +1.8 V.
Connect to ground.
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6P30006A REV D 061711
IDT6P30006A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
Pin
Number
17
18
Pin
Name
OUT4
OUT3
OUT2
OUT1
VDD
GND
TCXO_INA
VDD
Pin
Type
Output
Output
Output
Output
Power
Power
Input
Power
Pin Description
Buffered output. Outputs tri-state with weak pull-down when disabled.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Buffered output. Outputs tri-state with weak pull-down when disabled.
Connect to +1.8 V.
Connect to ground.
Connect to 13 MHz TCXO input.
Connect to +1.8 V.
19
20
21
22
23
24
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6P30006A REV D 061711
IDT6P30006A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
General I
2
C Serial Interface
How to Write:
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D2
(H)
IDT clock will
acknowledge
Controller (host) sends the beginning byte location =N
IDT clock will
acknowledge
Controller (host) sends the data byte count = X
IDT clock will
acknowledge
Controller (host) starts sending
Byte N through Byte N + X - 1
(see Note 2)
IDT clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D2
(H)
IDT clock will
acknowledge
Controller (host) sends the beginning byte location =N
IDT clock will
acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address D3
(H)
IDT clock will
acknowledge
Controller (host) sends the data byte count = X
IDT clock sends
Byte N + X - 1
IDT clock sends
Byte 0 through byte X (if X
(H)
was written to
byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
T
WR
starTbit
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte = N
O
O
O
Byte N + X - 1
ACK
P
stoP bit
.
X
B
Y
T
E
ACK
ACK
O
O
O
O
O
O
N
P
ACK
.
X
B
Y
T
E
Beginning Byte N
O
O
O
Byte N + X - 1
Data Byte Count = X
RT
RD
Slave Address D2
(H)
Beginning Byte = N
ACK
IDT (Slave/Receiver)
Controller (Host)
T
WR
starTbit
Slave Address D2
(H)
WRite
ACK
IDT (Slave/Receiver)
Repeat starT
ReaD
ACK
Slave Address D3
(H)
Not acknowledge
stoP bit
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6P30006A REV D 061711
IDT6P30006A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
I
2
C Address
The IDT6P30006A is a slave-only device that supports block read and block write protocol using a single 7 bit address and
read/write bit. A block write (D2
(H)
) or block read (D3
(H)
) is made up of seven (7) bits and one (1) read/write bit.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W#
X
In applications where the indexed block write and block read
are used, the dummy byte (bit 11-18) functions as a
register-offset (8 bits) pointer.
Byte 0: Control Register
Bit
7
6
5
4
3
2
1
0
Description
Reserved
Reserved
Reserved
Reserved
OE for clock output
OE for clock output
OE for clock output
OE for clock output
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up
Condition
Undefined
Undefined
Undefined
Undefined
1
1
1
1
Output(s) Affected
Not applicable
Not applicable
Not applicable
Not applicable
Notes
Output_5 clock output
Output_6 clock output
Output_7 clock output
Output_8 clock output
1=enabled
0=disabled
1=enabled
0=disabled
1=enabled
0=disabled
1=enabled
0=disabled
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6P30006A REV D 061711