5962-8957601-XXA datasheet, PDF

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5962-8957601-XXA: DescriptionRemote Terminal with RAM; File Size918KB，44 Pages; ManufacturerETC

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5962-8957601-XXA Overview

Remote Terminal with RAM

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UT1553B RTR Remote Terminal with RAM

EATURES

Complete MIL-STD-1553B remote terminal interface

1K x 16 of on-chip static RAM for message data,

completely accessible to host

Self-test capability, including continuous loop-back

compare

Programmable memory mapping via pointers for

efﬁcient use of internal memory, including buffering

multiple messages per subaddress

RT-RT Terminal Address Compare

Command word stored with incoming data for

enhanced data management

User selectable RAM Busy (RBUSY) signal for slow

or fast processor interfacing

Full military operating temperature range, -55°C to

+125°C, screened to the speciﬁc test methods listed in

Table I of MIL-STD-883, Method 5004, Class B, also

Standard Military Drawing available

Available in 68-pin pingrid array package

NTRODUCTION

The UT1553B RTR is a monolithic CMOS VLSI solution

to the requirements of the dual-redundant MIL-STD-1553B

interface. Designed to reduce cost and space, the RTR

integrates the remote terminal logic with a user-conﬁgured

1K x 16 static RAM. In addition, the RTR has a ﬂexible

subsystem interface to permit use with most processors or

controllers.

The RTR provides all protocol, data handling, error

checking, and memory control functions, as well as

comprehensive self-test capabilities. The RTR’s memory

meets all of MIL-STD-1553B message storage needs

through user-deﬁned memory mapping. This memory-

mapped architecture allows multiple message buffering at

MCSA(4:0)

MODE CODE/

SUBADDRESS

OUTPUT MULTIPLEXING AND

SELF-TEST WRAPAROUND LOGIC

OUT

RTA(4:0)

REMOTE TERMINAL

ADDRESS

CONTROL

INPUTS

STATUS

OUTPUTS

DECODER

COMMAND

RECOGNITION

CONTROL AND

ERROR LOGIC

1K X 16 RAM

ADDR(9:0)

MUX

ENCODER

PTR REGISTER

OUT

DECODER

12MHz

DATA(15:0)

2MHz

RESET

Figure 1. UT1553B RTR Functional Block Diagram

RTR-1

Table of Contents

1.0

ARCHITECTURE AND OPERATION.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 RTR RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.5 MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . . .9

1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

MEMORY MAP EXAMPLE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.0

3.0

PIN IDENTIFICATION AND DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.0

MAXIMUM AND RECOMMENDED OPERATING CONDITIONS.

. . . . . . . . . . . . . . . . 19

5.0

DC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.0

AC ELECTRICAL CHARACTERISTICS.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.0

PACKAGE OUTLINE DRAWING

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

RTR-2

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