EP1K50TI144-2 datasheet, PDF - EEWORLD Datasheet

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EP1K50TI144-2: DescriptionFPGA - Field Programmable Gate Array FPGA - ACEX 1K 360 LABs 102 IOs; CategoryProgrammable logic devices Programmable logic; File Size1MB，86 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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FPGA - Field Programmable Gate Array FPGA - ACEX 1K 360 LABs 102 IOs

EP1K50TI144-2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
package instruction	TQFP-144
Reach Compliance Code	compliant
ECCN code	3A991
Is Samacsys	N
maximum clock frequency	37.5 MHz
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Number of I/O lines	102
Number of entries	102
Number of logical units	2880
Output times	102
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	102 I/O
Output function	MIXED
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	220
power supply	2.5,2.5/3.3 V
Programmable logic type	LOADABLE PLD
propagation delay	0.4 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	20 mm
Base Number Matches	1

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ACEX 1K

Programmable Logic Device Family

Data Sheet

May 2003, ver. 3.4

Features...

■

Programmable logic devices (PLDs), providing low cost

system-on-a-programmable-chip (SOPC) integration in a single

device

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

–

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

–

Logic array for general logic functions

High density

–

10,000 to 100,000 typical gates (see

Table 1)

–

Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be

used without reducing logic capacity)

Cost-efficient programmable architecture for high-volume

applications

–

Cost-optimized process

–

Low cost solution for high-performance communications

applications

System-level features

–

MultiVolt

I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

–

Bidirectional I/O performance (setup time [t

] and clock-to-

output delay [t

]) up to 250 MHz

–

Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG)

PCI Local Bus Specification,

Revision 2.2

for 3.3-V operation at 33 MHz or 66 MHz

Extended temperature range

Tools

Table 1. ACEX

1K Device Features

Feature

Typical gates

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

Maximum user I/O pins

EP1K10

10,000

56,000

576

12,288

136

EP1K30

30,000

119,000

1,728

24,576

171

EP1K50

50,000

199,000

2,880

40,960

249

EP1K100

100,000

257,000

4,992

49,152

333

Altera Corporation

DS-ACEX-3.4

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